MIPS: Netlogic: Avoid unnecessary cache flushes
authorJayachandran C <jayachandranc@netlogicmicro.com>
Tue, 23 Aug 2011 08:05:51 +0000 (13:35 +0530)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 7 Dec 2011 22:04:54 +0000 (22:04 +0000)
XLR dcache is fully coherent across CPUs, so avoid unnecessary dcache
flushes.

Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2729/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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