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clk / highbank: Prevent glitches in non-bypass reset mode
authorMark Langsdorf <mark.langsdorf@calxeda.com>
Mon, 28 Jan 2013 16:13:13 +0000 (16:13 +0000)
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>
Fri, 1 Feb 2013 23:01:15 +0000 (00:01 +0100)
The highbank clock will glitch with the current code if the
clock rate is reset without relocking the PLL. Program the PLL
correctly to prevent glitches.

Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

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