clk: shmobile: rcar-gen2: Fix clock parent for all non-PLL clocks

The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as
their parent, not the main clock. Fix it.

This bug introduced in v3.14-rc1 breaks various devices on the Lager and
Kolesh shmobile boards and should thus be considered as a regression for
which a fix during the -rc series is appropriate.

Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>

diff --cc drivers/clk/shmobile/clk-rcar-gen2.c
Simple merge