xloader: Panda - clean board files style

Solve checkpatch in ./board/omap4430panda/* and ./cpu/omap4

Ignore volatile warnings and mux define crap because it will
be solved in following patches separately

Signed-off-by: Andy Green <andy.green@linaro.org>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>

diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
index a83f1c6..80432f4 100644 (file)
--- a/board/omap4430panda/clock.c
+++ b/board/omap4430panda/clock.c
@@ -72,7 +72,7 @@ struct dpll_param mpu_dpll_param[7] = {
 #elif CONFIG_MPU_1000
        {0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
 #else
-       {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},       
+       {0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
 #endif
 };
 
@@ -150,7 +150,7 @@ struct dpll_param core_dpll_param_l3_190[7] = {
        {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
        /* 38.4M values */
 #ifdef CONFIG_OMAP4_SDC
-#ifdef CORE_190MHZ 
+#ifdef CORE_190MHZ
        {0x1f0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
 #else /* Default CORE @166MHz */
        {0x1b0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
@@ -226,11 +226,9 @@ struct dpll_param usb_dpll_param[7] = {
 #endif
 };
 
-typedef struct dpll_param dpll_param;
-
 static void configure_mpu_dpll(u32 clk_index)
 {
-       dpll_param *dpll_param_p;
+       struct dpll_param *dpll_param_p;
 
        /* Unlock the MPU dpll */
        sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_MN_POWER_BYPASS);
@@ -256,7 +254,7 @@ static void configure_mpu_dpll(u32 clk_index)
 
 static void configure_iva_dpll(u32 clk_index)
 {
-       dpll_param *dpll_param_p;
+       struct dpll_param *dpll_param_p;
 
        /* Unlock the IVA dpll */
        sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_MN_POWER_BYPASS);
@@ -281,13 +279,11 @@ static void configure_iva_dpll(u32 clk_index)
        /* Lock the iva dpll */
        sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_LOCK);
        wait_on_value(BIT0, 1, CM_IDLEST_DPLL_IVA, LDELAY);
-
-       return;
 }
 
 static void configure_per_dpll(u32 clk_index)
 {
-       dpll_param *dpll_param_p;
+       struct dpll_param *dpll_param_p;
 
        /* Unlock the PER dpll */
        sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_MN_POWER_BYPASS);
@@ -308,27 +304,22 @@ static void configure_per_dpll(u32 clk_index)
        sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param_p->m6);
        sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param_p->m7);
 
-//     if(omap_revision() == OMAP4430_ES1_0)
-//     {
-               /* Do this only on ES1.0 */
-               sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1);
-               sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1);
-               sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1);
-               sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1);
-               sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1);
-               sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1);
-//     }
+
+       sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1);
+       sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1);
+       sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1);
+       sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1);
+       sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1);
+       sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1);
 
        /* Lock the per dpll */
        sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_LOCK);
        wait_on_value(BIT0, 1, CM_IDLEST_DPLL_PER, LDELAY);
-
-       return;
 }
 
 static void configure_abe_dpll(u32 clk_index)
 {
-       dpll_param *dpll_param_p;
+       struct dpll_param *dpll_param_p;
 
        /* Select sys_clk as ref clk for ABE dpll */
        sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0);
@@ -361,13 +352,11 @@ static void configure_abe_dpll(u32 clk_index)
        /* Lock the abe dpll */
        sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_LOCK);
        wait_on_value(BIT0, 1, CM_IDLEST_DPLL_ABE, LDELAY);
-
-       return;
 }
 
 static void configure_usb_dpll(u32 clk_index)
 {
-       dpll_param *dpll_param_p;
+       struct dpll_param *dpll_param_p;
 
        /* Select the 60Mhz clock 480/8 = 60*/
        sr32(CM_CLKSEL_USB_60MHz, 0, 32, 0x1);
@@ -397,13 +386,11 @@ static void configure_usb_dpll(u32 clk_index)
 
        /* force enable the CLKDCOLDO clock */
        sr32(CM_CLKDCOLDO_DPLL_USB, 0, 32, 0x100);
-
-       return;
 }
 
 static void configure_core_dpll(clk_index)
 {
-       dpll_param *dpll_param_p;
+       struct dpll_param *dpll_param_p;
 
        /* Get the sysclk speed from cm_sys_clksel
         * Set it to 38.4 MHz, in case ROM code is bypassed
@@ -419,12 +406,17 @@ static void configure_core_dpll(clk_index)
        wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);
 
        /* Program Core DPLL */
-       if(omap_revision() == OMAP4430_ES1_0)
+       switch (omap_revision()) {
+       case OMAP4430_ES1_0:
                dpll_param_p = &core_dpll_param_l3_190[clk_index];
-       else if(omap_revision() == OMAP4430_ES2_0)
+               break;
+       case OMAP4430_ES2_0:
                dpll_param_p = &core_dpll_param[clk_index];
-       else if(omap_revision() >= OMAP4430_ES2_1)
+               break;
+       case OMAP4430_ES2_1:
                dpll_param_p = &core_dpll_param_ddr400[clk_index];
+               break;
+       }
 
        /* Disable autoidle */
        sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
@@ -438,8 +430,7 @@ static void configure_core_dpll(clk_index)
        sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
        sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
 
-       if(omap_revision() == OMAP4430_ES1_0)
-       {
+       if (omap_revision() == OMAP4430_ES1_0) {
                /* Do this only on ES1.0 */
                sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
                sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
@@ -449,24 +440,21 @@ static void configure_core_dpll(clk_index)
                sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
        }
 
-
        /* Lock the core dpll */
        sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);
        wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
-
-       return;
 }
 
 
 void configure_core_dpll_no_lock(void)
 {
-       dpll_param *dpll_param_p;
+       struct dpll_param *dpll_param_p;
        u32 clk_index;
 
        /* Get the sysclk speed from cm_sys_clksel
         * Set it to 38.4 MHz, in case ROM code is bypassed
         */
-       __raw_writel(0x7,CM_SYS_CLKSEL);
+       __raw_writel(0x7, CM_SYS_CLKSEL);
        clk_index = 7;
 
        clk_index = clk_index - 1;
@@ -478,12 +466,17 @@ void configure_core_dpll_no_lock(void)
        wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);
 
        /* Program Core DPLL */
-       if(omap_revision() == OMAP4430_ES1_0)
+       switch (omap_revision()) {
+       case OMAP4430_ES1_0:
                dpll_param_p = &core_dpll_param_l3_190[clk_index];
-       else if(omap_revision() == OMAP4430_ES2_0)
+               break;
+       case OMAP4430_ES2_0:
                dpll_param_p = &core_dpll_param[clk_index];
-       else if(omap_revision() >= OMAP4430_ES2_1)
+               break;
+       case OMAP4430_ES2_1:
                dpll_param_p = &core_dpll_param_ddr400[clk_index];
+               break;
+       }
 
        /* Disable autoidle */
        sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
@@ -497,18 +490,12 @@ void configure_core_dpll_no_lock(void)
        sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
        sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
 
-//     if(omap_revision() == OMAP4430_ES1_0)
-//     {
-               /* Do this only on ES1.0 */
-               sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
-               sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
-               sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
-               sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
-               sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x0);
-               sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
-//     }
-
-       return;
+       sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
+       sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
+       sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
+       sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
+       sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x0);
+       sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
 }
 
 void lock_core_dpll(void)
@@ -516,22 +503,26 @@ void lock_core_dpll(void)
        /* Lock the core dpll */
        sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);
        wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
-
-       return;
 }
 
 void lock_core_dpll_shadow(void)
 {
-       dpll_param *dpll_param_p;
+       struct dpll_param *dpll_param_p;
+
        /* Lock the core dpll using freq update method */
-       *(volatile int*)0x4A004120 = 10;        //(CM_CLKMODE_DPLL_CORE)
+       *(volatile int*)0x4A004120 = 10;        /* CM_CLKMODE_DPLL_CORE */
 
-       if(omap_revision() == OMAP4430_ES1_0)
+       switch (omap_revision()) {
+       case OMAP4430_ES1_0:
                dpll_param_p = &core_dpll_param_l3_190[6];
-       else if(omap_revision() == OMAP4430_ES2_0)
+               break;
+       case OMAP4430_ES2_0:
                dpll_param_p = &core_dpll_param[6];
-       else if(omap_revision() >= OMAP4430_ES2_1)
+               break;
+       case OMAP4430_ES2_1:
                dpll_param_p = &core_dpll_param_ddr400[6];
+               break;
+       }
 
        /* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
         * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1
@@ -539,13 +530,12 @@ void lock_core_dpll_shadow(void)
        *(volatile int*)0x4A004260 = 0x70D | (dpll_param_p->m2 << 11);
 
        /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */
-       while( ( (*(volatile int*)0x4A004260) & 0x1) == 0x1 );
+       while (((*(volatile int*)0x4A004260) & 0x1) == 0x1)
+               ;
 
        /* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */
        wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
-       //lock_core_dpll();
-
-       return;
+       /* lock_core_dpll(); */
 }
 
 static void enable_all_clocks(void)
@@ -557,7 +547,10 @@ static void enable_all_clocks(void)
        sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
 
        wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
-       //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY);
+       /*
+        * wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL,
+        *      LDELAY);
+        */
 
        /* Enable ivahd and sl2 clocks */
        sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
@@ -567,9 +560,9 @@ static void enable_all_clocks(void)
        wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
 
        /* wait for ivahd to become accessible */
-       //wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY); */
        /* wait for sl2 to become accessible */
-       //wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY); */
 
        /* Enable Tesla clocks */
        sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
@@ -578,43 +571,43 @@ static void enable_all_clocks(void)
        wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
 
        /* wait for tesla to become accessible */
-       //wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY); */
 
        /* TODO: Some hack needed by MM: Clean this */
        #if 0 /* Doesn't work on some Zebu */
-       *(volatile int*)0x4a306910 = 0x00000003;
-       *(volatile int*)0x550809a0 = 0x00000001;
-       *(volatile int*)0x55080a20 = 0x00000007;
+       *(volatile int *)0x4a306910 = 0x00000003;
+       *(volatile int *)0x550809a0 = 0x00000001;
+       *(volatile int *)0x55080a20 = 0x00000007;
        #endif
 
        /* ABE clocks */
        sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
        sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY); */
        sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY); */
        sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY); */
        sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY); */
        sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
-       //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY); */
        sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
-       //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY); */
        sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
-       //wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY); */
        sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
-       //wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY); */
        sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY); */
        sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY); */
        sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY); */
        sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY); */
        sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY); */
        /* Disable sleep transitions */
        sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
 
@@ -634,7 +627,7 @@ static void enable_all_clocks(void)
        wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY);
 
        /* GPIO clocks */
-       sr32(CM_L4PER_GPIO2_CLKCTRL, 0 ,32, 0x1);
+       sr32(CM_L4PER_GPIO2_CLKCTRL, 0, 32, 0x1);
        wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY);
        sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1);
        wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY);
@@ -673,10 +666,12 @@ static void enable_all_clocks(void)
        /* MMC clocks */
        sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2);
        sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1);
-       //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC1_CLKCTRL, LDELAY);
+       /*wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC1_CLKCTRL,
+        *      LDELAY); */
        sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2);
        sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1);
-       //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC2_CLKCTRL, LDELAY);
+       /*wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC2_CLKCTRL,
+        *      LDELAY); */
        sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2);
        wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY);
        sr32(CM_L4PER_MMCSD4_CLKCTRL, 0, 32, 0x2);
@@ -726,48 +721,54 @@ static void enable_all_clocks(void)
        /* Enable Camera clocks */
        sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
        sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
-       //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY); */
        sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY); */
        sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
 
        /* Enable DSS clocks */
        /* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
-       *(volatile int*)0x4A307100 = 0x7; //DSS_PRM
+       *(volatile int *)0x4A307100 = 0x7; /* DSS_PRM */
        sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
        sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
-       //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY); */
        sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY); */
+
        /* Check for DSS Clocks */
-       while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00)
-       /* Set HW_AUTO transition mode */
-       sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
+       while (((*(volatile int *)0x4A009100) & 0xF00) != 0xE00)
+               /* Set HW_AUTO transition mode */
+               sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
 
        /* Enable SGX clocks */
        sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
        sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY); */
        /* Check for SGX FCLK and ICLK */
-       while ( (*(volatile int*)0x4A009200) != 0x302 );
-       //sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0);
+       while ((*(volatile int *)0x4A009200) != 0x302)
+               ;
+       /* sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0); */
        /* Enable hsi/unipro/usb clocks */
        sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
-       //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL,
+        *      LDELAY); */
        sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL,
+        *      LDELAY); */
        sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL,
+        *      LDELAY); */
        sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
-       //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL,
+        *      LDELAY); */
        sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
-       //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY); */
        sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
-       //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY);
+       /* wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL,
+        *      LDELAY); */
        /* enable the 32K, 48M optional clocks and enable the module */
        sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
-       //wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
-       return;
+       /* wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY); */
 }
 
 /******************************************************************************
@@ -781,7 +782,7 @@ void prcm_init(void)
        /* Get the sysclk speed from cm_sys_clksel
         * Set the CM_SYS_CLKSEL in case ROM code has not set
         */
-       __raw_writel(0x7,CM_SYS_CLKSEL);
+       __raw_writel(0x7, CM_SYS_CLKSEL);
        clk_index = readl(CM_SYS_CLKSEL);
        if (!clk_index)
                return; /* Sys clk uninitialized */
@@ -799,6 +800,4 @@ void prcm_init(void)
        /* Enable all clocks */
        enable_all_clocks();
 #endif
-
-       return;
 }

diff --git a/board/omap4430panda/omap4430panda.c b/board/omap4430panda/omap4430panda.c
index a91e2aa..0278032 100644 (file)
--- a/board/omap4430panda/omap4430panda.c
+++ b/board/omap4430panda/omap4430panda.c
@@ -103,8 +103,8 @@
 #define MR1_NWR7                       5
 #define MR1_NWR8                       6
 
-#define MR1_VALUE      (MR1_NWR3 << 5) | (MR1_WC << 4) | (MR1_BT_SEQ << 3)  \
-                                                       | (MR1_BL8 << 0)
+#define MR1_VALUE      ((MR1_NWR3 << 5) | (MR1_WC << 4) | (MR1_BT_SEQ << 3)  \
+                                                       | (MR1_BL8 << 0))
 
 /* defines for MR2 */
 #define MR2_RL3_WL1                    1
@@ -234,7 +234,7 @@ static inline void delay(unsigned long loops)
 void big_delay(unsigned int count)
 {
        int i;
-       for (i=0; i<count; i++)
+       for (i = 0; i < count; i++)
                delay(1);
 }
 
@@ -248,7 +248,7 @@ static int emif_config(unsigned int base)
        const struct ddr_regs *ddr_regs;
        rev = omap_revision();
 
-       if(rev == OMAP4430_ES1_0)
+       if (rev == OMAP4430_ES1_0)
                ddr_regs = &ddr_regs_380_mhz;
        else if (rev == OMAP4430_ES2_0)
                ddr_regs = &ddr_regs_200_mhz_2cs;
@@ -261,7 +261,7 @@ static int emif_config(unsigned int base)
         * EMIF_SDRAM_CONFIG[13:10] REG_CL = 3
         * EMIF_SDRAM_CONFIG[6:4] REG_IBANK = 3 - 8 banks
         * EMIF_SDRAM_CONFIG[3] REG_EBANK = 0 - CS0
-        * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2  - 512- 9 column
+        * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2  - 512- 9 column
         * JDEC specs - S4-2Gb --8 banks -- R0-R13, C0-c8
         */
        *(volatile int*)(base + EMIF_LPDDR2_NVM_CONFIG) &= 0xBFFFFFFF;
@@ -373,8 +373,7 @@ static void ddr_init(void)
        unsigned int base_addr, rev;
        rev = omap_revision();
 
-       if (rev == OMAP4430_ES1_0)
-       {
+       if (rev == OMAP4430_ES1_0) {
                /* Configurte the Control Module DDRIO device */
                __raw_writel(0x1c1c1c1c, 0x4A100638);
                __raw_writel(0x1c1c1c1c, 0x4A10063c);
@@ -446,7 +445,7 @@ static void ddr_init(void)
        /* PHY control values */
 
        sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
-        sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
+       sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
 
        /* Put the Core Subsystem PD to ON State */
 
@@ -505,7 +504,7 @@ int board_init(void)
 u32 get_mem_type(void)
 {
        /* no nand, so return GPMC_NONE */
-       return GPMC_NONE;       
+       return GPMC_NONE;
 }
 
 /*****************************************
@@ -640,20 +639,29 @@ void s_init(void)
 #endif 
        prcm_init();
 
-       if(rev != OMAP4430_ES1_0) {
+       if (rev != OMAP4430_ES1_0) {
                if (__raw_readl(0x4805D138) & (1<<22)) {
-                       sr32(0x4A30a31C, 8, 1, 0x1);  /* enable software ioreq */
-                       sr32(0x4A30a31C, 1, 2, 0x0);  /* set for sys_clk (38.4MHz) */
-                       sr32(0x4A30a31C, 16, 4, 0x1); /* set divisor to 2 */
-                       sr32(0x4A30a110, 0, 1, 0x1);  /* set the clock source to active */
-                       sr32(0x4A30a110, 2, 2, 0x3);  /* enable clocks */
-               }
-               else {
-                       sr32(0x4A30a314, 8, 1, 0x1); /* enable software ioreq */
-                       sr32(0x4A30a314, 1, 2, 0x2); /* set for PER_DPLL */
-                       sr32(0x4A30a314, 16, 4, 0xf); /* set divisor to 16 */
-                       sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */
-                       sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */
+                       /* enable software ioreq */
+                       sr32(0x4A30a31C, 8, 1, 0x1);
+                       /* set for sys_clk (38.4MHz) */
+                       sr32(0x4A30a31C, 1, 2, 0x0);
+                       /* set divisor to 2 */
+                       sr32(0x4A30a31C, 16, 4, 0x1);
+                       /* set the clock source to active */
+                       sr32(0x4A30a110, 0, 1, 0x1);
+                       /* enable clocks */
+                       sr32(0x4A30a110, 2, 2, 0x3);
+               } else {
+                       /* enable software ioreq */
+                       sr32(0x4A30a314, 8, 1, 0x1);
+                       /* set for PER_DPLL */
+                       sr32(0x4A30a314, 1, 2, 0x2);
+                       /* set divisor to 16 */
+                       sr32(0x4A30a314, 16, 4, 0xf);
+                       /* set the clock source to active */
+                       sr32(0x4A30a110, 0, 1, 0x1);
+                       /* enable clocks */
+                       sr32(0x4A30a110, 2, 2, 0x3);
                }
        }
 
@@ -1222,7 +1230,7 @@ void update_mux(u32 btype, u32 mtype)
 }
 
 /* optionally do something like blinking LED */
-void board_hang (void)
+void board_hang(void)
 { while (0) {};}
 
 int nand_init(void)

diff --git a/board/omap4430panda/syslib.c b/board/omap4430panda/syslib.c
index 2b16cc4..9b91a54 100644 (file)
--- a/board/omap4430panda/syslib.c
+++ b/board/omap4430panda/syslib.c
@@ -37,8 +37,8 @@
  *************************************************************/
 void sdelay(unsigned long loops)
 {
-       __asm__ volatile ("1:\n" "subs %0, %1, #1\n"  
-                                         "bne 1b":"=r" (loops):"0"(loops));
+       __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+                                         "bne 1b" : "=r" (loops) : "0"(loops));
 }
 
 /*****************************************************************
@@ -65,9 +65,9 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
                ++i;
                val = __raw_readl(read_addr) & read_bit_mask;
                if (val == match_value)
-                       return (1);
+                       return 1;
                if (i == bound)
-                       return (0);
+                       return 0;
        } while (1);
 }
 

diff --git a/cpu/omap4/cpu.c b/cpu/omap4/cpu.c
index 7306fc1..b8f231d 100644 (file)
--- a/cpu/omap4/cpu.c
+++ b/cpu/omap4/cpu.c
@@ -45,7 +45,7 @@
 #define C1_HIGH_VECTORS        (1<<13) /* location of vectors: low/high addresses */
 #define RESERVED_1     (0xf << 3)      /* must be 111b for R/W */
 
-int cpu_init (void)
+int cpu_init(void)
 {
        return 0;
 }
@@ -63,20 +63,23 @@ unsigned int cortex_a9_rev(void)
 
 unsigned int omap_revision(void)
 {
-       unsigned int chip_rev = 0;
-       unsigned int rev = cortex_a9_rev();
+       switch (cortex_a9_rev()) {
 
-       switch(rev) {
        case 0x410FC091:
                return OMAP4430_ES1_0;
+
        case 0x411FC092:
-               chip_rev = (__raw_readl(OMAP44XX_CTRL_ID_CODE)  >> 28) & 0xF;
-               if (chip_rev == 3)
+               switch ((__raw_readl(OMAP44XX_CTRL_ID_CODE) >> 28) & 0xF) {
+               case 0:
+               case 1:
+               case 2:
+                       return OMAP4430_ES2_0;
+               case 3:
                        return OMAP4430_ES2_1;
-               else if (chip_rev >= 4)
+               default:
                        return OMAP4430_ES2_2;
-               else
-                       return OMAP4430_ES2_0;
+               }
        }
+
        return OMAP4430_SILICON_ID_INVALID;
 }

diff --git a/cpu/omap4/mmc.c b/cpu/omap4/mmc.c
index 6842402..00d07da 100644 (file)
--- a/cpu/omap4/mmc.c
+++ b/cpu/omap4/mmc.c
@@ -52,7 +52,7 @@ static block_dev_desc_t mmc_blk_dev;
 
 block_dev_desc_t *mmc_get_dev(int dev)
 {
-       return ((block_dev_desc_t *) &mmc_blk_dev);
+       return (block_dev_desc_t *)&mmc_blk_dev;
 }
 
 unsigned char mmc_board_init(void)
@@ -107,8 +107,8 @@ unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div)
        mmc_reg_out(OMAP_HSMMC_SYSCTL,
                    ICE_MASK | CLKD_MASK, (val << CLKD_OFFSET) | ICE_OSCILLATE);
 
-       while ((OMAP_HSMMC_SYSCTL & ICS_MASK) == ICS_NOTREADY) {
-       }
+       while ((OMAP_HSMMC_SYSCTL & ICS_MASK) == ICS_NOTREADY)
+               ;
 
        OMAP_HSMMC_SYSCTL |= CEN_ENABLE;
        return 1;
@@ -121,10 +121,12 @@ unsigned char mmc_init_setup(void)
        mmc_board_init();
 
        OMAP_HSMMC_SYSCONFIG |= MMC_SOFTRESET;
-       while ((OMAP_HSMMC_SYSSTATUS & RESETDONE) == 0) ;
+       while ((OMAP_HSMMC_SYSSTATUS & RESETDONE) == 0)
+               ;
 
        OMAP_HSMMC_SYSCTL |= SOFTRESETALL;
-       while ((OMAP_HSMMC_SYSCTL & SOFTRESETALL) != 0x0) ;
+       while ((OMAP_HSMMC_SYSCTL & SOFTRESETALL) != 0x0)
+               ;
 
        OMAP_HSMMC_HCTL = DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0;
        OMAP_HSMMC_CAPA |= VS30_3V0SUP | VS18_1V8SUP;
@@ -141,6 +143,7 @@ unsigned char mmc_init_setup(void)
        OMAP_HSMMC_IE = 0x307f0033;
 
        mmc_init_stream();
+
        return 1;
 }
 
@@ -149,8 +152,8 @@ unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg,
 {
        volatile unsigned int mmc_stat;
 
-       while ((OMAP_HSMMC_PSTATE & DATI_MASK) == DATI_CMDDIS) {
-       }
+       while ((OMAP_HSMMC_PSTATE & DATI_MASK) == DATI_CMDDIS)
+               ;
 
        OMAP_HSMMC_BLK = BLEN_512BYTESLEN | NBLK_STPCNT;
        OMAP_HSMMC_STAT = 0xFFFFFFFF;
@@ -507,28 +510,26 @@ unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt,
 
 int mmc_init(int verbose)
 {
-       unsigned char ret;
+       unsigned char ret = configure_mmc(&cur_card_data);
 
-       ret = configure_mmc(&cur_card_data);
+       if (ret != 1)
+               return 0;
 
-       if (ret == 1) {
-               mmc_blk_dev.if_type = IF_TYPE_MMC;
-               mmc_blk_dev.part_type = PART_TYPE_DOS;
-               mmc_blk_dev.dev = 0;
-               mmc_blk_dev.lun = 0;
-               mmc_blk_dev.type = 0;
+       mmc_blk_dev.if_type = IF_TYPE_MMC;
+       mmc_blk_dev.part_type = PART_TYPE_DOS;
+       mmc_blk_dev.dev = 0;
+       mmc_blk_dev.lun = 0;
+       mmc_blk_dev.type = 0;
 
-               /* FIXME fill in the correct size (is set to 32MByte) */
-               mmc_blk_dev.blksz = MMCSD_SECTOR_SIZE;
-               mmc_blk_dev.lba = 0x10000;
-               mmc_blk_dev.removable = 0;
-               mmc_blk_dev.block_read = mmc_bread;
+       /* FIXME fill in the correct size (is set to 32MByte) */
+       mmc_blk_dev.blksz = MMCSD_SECTOR_SIZE;
+       mmc_blk_dev.lba = 0x10000;
+       mmc_blk_dev.removable = 0;
+       mmc_blk_dev.block_read = mmc_bread;
 
-               fat_register_device(&mmc_blk_dev, 1);
-               return 1;
-       }
-       else 
-               return 0;
+       fat_register_device(&mmc_blk_dev, 1);
+
+       return 1;
 }
 
 int mmc_read(ulong src, uchar *dst, int size)

diff --git a/cpu/omap4/start.S b/cpu/omap4/start.S
index 65f168a..0e11fcc 100644 (file)
--- a/cpu/omap4/start.S
+++ b/cpu/omap4/start.S
@@ -47,7 +47,7 @@ _start:
 
 _hang:
        .word do_hang
-       
+
        .word 0x12345678
        .word 0x12345678
        .word 0x12345678