arch: arm: dts: agilex5: Set SDIO_SEL GPIO pin as output

Use GPIO hogging method in device tree to set SDIO_SEL pin (portb3)
direction as output with value 0 after power-on reset.

This is to ensure stable 0V voltage reading from SDIO_SEL GPIO pin
after board init.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>

diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index 8d6503d..b34af85 100644 (file)
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -673,6 +673,17 @@
        bootph-all;
 };
 
+&gpio1 {
+       /* Configure GPIO 1 pin 3 as output pin with value 0 during GPIO probe */
+       portb: gpio-controller@0{
+               sdio_sel {
+                       gpio-hog;
+                       gpios = <3 GPIO_ACTIVE_HIGH>;
+                       output-low;
+               };
+       };
+};
+
 &i2c0 {
        reset-names = "i2c";
 };

diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig
index 79c3f03..4ac0a5d 100644 (file)
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex5_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_TEXT_BASE=0x80200000
+CONFIG_SPL_GPIO=y
 CONFIG_NR_DRAM_BANKS=3
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80300000
@@ -75,6 +76,8 @@ CONFIG_BOOTFILE="kernel.itb"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_GPIO_HOG=y
+CONFIG_SPL_GPIO_HOG=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_DW=y