arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA

Add SPL support for Agilex5 SoCFPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index cccba71..22d48df 100644 (file)
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -66,6 +66,8 @@ obj-y += wrap_handoff_soc64.o
 obj-y  += wrap_pll_config_soc64.o
 obj-y  += altera-sysmgr.o
 obj-y  += ccu_ncore3.o
+obj-y  += system_manager_soc64.o
+obj-y  += timer_s10.o
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_N5X
@@ -109,6 +111,7 @@ obj-y       += spl_n5x.o
 endif
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
 obj-y  += spl_soc64.o
+obj-y  += spl_agilex5.o
 endif
 else
 obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o

diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c
new file mode 100644 (file)
index 0000000..c87e9ed
--- /dev/null
+++ b/arch/arm/mach-socfpga/spl_agilex5.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
+ *
+ */
+
+#include <init.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <hang.h>
+#include <spl.h>
+#include <asm/arch/base_addr_soc64.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <wdt.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong dummy)
+{
+       int ret;
+       struct udevice *dev;
+
+       ret = spl_early_init();
+       if (ret)
+               hang();
+
+       socfpga_get_sys_mgr_addr("sysmgr@10d12000");
+       socfpga_get_managers_addr();
+
+       sysmgr_pinmux_init();
+
+       /* Ensure watchdog is paused when debugging is happening */
+       writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
+              socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+
+       timer_init();
+
+       ret = uclass_get_device(UCLASS_CLK, 0, &dev);
+       if (ret) {
+               debug("Clock init failed: %d\n", ret);
+               hang();
+       }
+
+       /*
+        * Enable watchdog as early as possible before initializing other
+        * component. Watchdog need to be enabled after clock driver because
+        * it will retrieve the clock frequency from clock driver.
+        */
+       if (CONFIG_IS_ENABLED(WDT))
+               initr_watchdog();
+
+       preloader_console_init();
+       print_reset_info();
+       cm_print_clock_quick_summary();
+
+       ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-ccu-config", &dev);
+       if (ret) {
+               printf("HPS CCU settings init failed: %d\n", ret);
+               hang();
+       }
+
+       ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-firewall-config", &dev);
+       if (ret) {
+               printf("HPS firewall settings init failed: %d\n", ret);
+               hang();
+       }
+
+       if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) {
+               ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+               if (ret) {
+                       debug("DRAM init failed: %d\n", ret);
+                       hang();
+               }
+       }
+
+       mbox_init();
+
+       if (IS_ENABLED(CONFIG_CADENCE_QSPI))
+               mbox_qspi_open();
+
+       /* Enable non secure access to ocram */
+       clrbits_le32(SOCFPGA_OCRAM_FIREWALL_ADDRESS + 0x18, BIT(0));
+}