*
* Copyright 2001 Compaq Computer Corporation.
* Copyright 2004-2005 Phil Blundell
- * Copyright 2007 OpenedHand Ltd.
+ * Copyright 2007-2008 OpenedHand Ltd.
*
* Authors: Phil Blundell <pb@handhelds.org>,
* Samuel Ortiz <sameo@openedhand.com>
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/irq.h>
+#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/mfd/asic3.h>
+struct asic3 {
+ void __iomem *mapping;
+ unsigned int bus_shift;
+ unsigned int irq_nr;
+ unsigned int irq_base;
+ spinlock_t lock;
+ u16 irq_bothedge[4];
+ struct gpio_chip gpio;
+ struct device *dev;
+};
+
+static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
+
static inline void asic3_write_register(struct asic3 *asic,
unsigned int reg, u32 value)
{
/* IRQs */
#define MAX_ASIC_ISR_LOOPS 20
-#define ASIC3_GPIO_Base_INCR \
- (ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base)
+#define ASIC3_GPIO_BASE_INCR \
+ (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
static void asic3_irq_flip_edge(struct asic3 *asic,
u32 base, int bit)
spin_lock_irqsave(&asic->lock, flags);
edge = asic3_read_register(asic,
- base + ASIC3_GPIO_EdgeTrigger);
+ base + ASIC3_GPIO_EDGE_TRIGGER);
edge ^= bit;
asic3_write_register(asic,
- base + ASIC3_GPIO_EdgeTrigger, edge);
+ base + ASIC3_GPIO_EDGE_TRIGGER, edge);
spin_unlock_irqrestore(&asic->lock, flags);
}
spin_lock_irqsave(&asic->lock, flags);
status = asic3_read_register(asic,
- ASIC3_OFFSET(INTR, PIntStat));
+ ASIC3_OFFSET(INTR, P_INT_STAT));
spin_unlock_irqrestore(&asic->lock, flags);
/* Check all ten register bits */
if (status & (1 << bank)) {
unsigned long base, istat;
- base = ASIC3_GPIO_A_Base
- + bank * ASIC3_GPIO_Base_INCR;
+ base = ASIC3_GPIO_A_BASE
+ + bank * ASIC3_GPIO_BASE_INCR;
spin_lock_irqsave(&asic->lock, flags);
istat = asic3_read_register(asic,
base +
- ASIC3_GPIO_IntStatus);
+ ASIC3_GPIO_INT_STATUS);
/* Clearing IntStatus */
asic3_write_register(asic,
base +
- ASIC3_GPIO_IntStatus, 0);
+ ASIC3_GPIO_INT_STATUS, 0);
spin_unlock_irqrestore(&asic->lock, flags);
for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
/* They start at bit 4 and go up */
if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
- desc = irq_desc + + i;
+ desc = irq_desc + asic->irq_base + i;
desc->handle_irq(asic->irq_base + i,
desc);
}
}
if (iter >= MAX_ASIC_ISR_LOOPS)
- printk(KERN_ERR "%s: interrupt processing overrun\n",
- __func__);
+ dev_err(asic->dev, "interrupt processing overrun\n");
}
static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
n = (irq - asic->irq_base) >> 4;
- return (n * (ASIC3_GPIO_B_Base - ASIC3_GPIO_A_Base));
+ return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
}
static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
index = asic3_irq_to_index(asic, irq);
spin_lock_irqsave(&asic->lock, flags);
- val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask);
+ val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
val |= 1 << index;
- asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val);
+ asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
spin_unlock_irqrestore(&asic->lock, flags);
}
spin_lock_irqsave(&asic->lock, flags);
regval = asic3_read_register(asic,
- ASIC3_INTR_Base +
- ASIC3_INTR_IntMask);
+ ASIC3_INTR_BASE +
+ ASIC3_INTR_INT_MASK);
regval &= ~(ASIC3_INTMASK_MASK0 <<
(irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
asic3_write_register(asic,
- ASIC3_INTR_Base +
- ASIC3_INTR_IntMask,
+ ASIC3_INTR_BASE +
+ ASIC3_INTR_INT_MASK,
regval);
spin_unlock_irqrestore(&asic->lock, flags);
}
index = asic3_irq_to_index(asic, irq);
spin_lock_irqsave(&asic->lock, flags);
- val = asic3_read_register(asic, bank + ASIC3_GPIO_Mask);
+ val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
val &= ~(1 << index);
- asic3_write_register(asic, bank + ASIC3_GPIO_Mask, val);
+ asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
spin_unlock_irqrestore(&asic->lock, flags);
}
spin_lock_irqsave(&asic->lock, flags);
regval = asic3_read_register(asic,
- ASIC3_INTR_Base +
- ASIC3_INTR_IntMask);
+ ASIC3_INTR_BASE +
+ ASIC3_INTR_INT_MASK);
regval |= (ASIC3_INTMASK_MASK0 <<
(irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
asic3_write_register(asic,
- ASIC3_INTR_Base +
- ASIC3_INTR_IntMask,
+ ASIC3_INTR_BASE +
+ ASIC3_INTR_INT_MASK,
regval);
spin_unlock_irqrestore(&asic->lock, flags);
}
spin_lock_irqsave(&asic->lock, flags);
level = asic3_read_register(asic,
- bank + ASIC3_GPIO_LevelTrigger);
+ bank + ASIC3_GPIO_LEVEL_TRIGGER);
edge = asic3_read_register(asic,
- bank + ASIC3_GPIO_EdgeTrigger);
+ bank + ASIC3_GPIO_EDGE_TRIGGER);
trigger = asic3_read_register(asic,
- bank + ASIC3_GPIO_TriggerType);
+ bank + ASIC3_GPIO_TRIGGER_TYPE);
asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
if (type == IRQT_RISING) {
edge &= ~bit;
} else if (type == IRQT_BOTHEDGE) {
trigger |= bit;
- if (asic3_gpio_get_value(asic, irq - asic->irq_base))
+ if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
edge &= ~bit;
else
edge |= bit;
* be careful to not unmask them if mask was also called.
* Probably need internal state for mask.
*/
- printk(KERN_NOTICE "asic3: irq type not changed.\n");
+ dev_notice(asic->dev, "irq type not changed\n");
}
- asic3_write_register(asic, bank + ASIC3_GPIO_LevelTrigger,
+ asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
level);
- asic3_write_register(asic, bank + ASIC3_GPIO_EdgeTrigger,
+ asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
edge);
- asic3_write_register(asic, bank + ASIC3_GPIO_TriggerType,
+ asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
trigger);
spin_unlock_irqrestore(&asic->lock, flags);
return 0;
.unmask = asic3_unmask_irq,
};
-static int asic3_irq_probe(struct platform_device *pdev)
+static int __init asic3_irq_probe(struct platform_device *pdev)
{
struct asic3 *asic = platform_get_drvdata(pdev);
unsigned long clksel = 0;
unsigned int irq, irq_base;
+ int map_size;
asic->irq_nr = platform_get_irq(pdev, 0);
if (asic->irq_nr < 0)
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
- asic3_write_register(asic, ASIC3_OFFSET(INTR, IntMask),
+ asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
ASIC3_INTMASK_GINTMASK);
set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
}
/* GPIOs */
-static inline u32 asic3_get_gpio(struct asic3 *asic, unsigned int base,
- unsigned int function)
-{
- return asic3_read_register(asic, base + function);
-}
-
-static void asic3_set_gpio(struct asic3 *asic, unsigned int base,
- unsigned int function, u32 bits, u32 val)
+static int asic3_gpio_direction(struct gpio_chip *chip,
+ unsigned offset, int out)
{
+ u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
+ unsigned int gpio_base;
unsigned long flags;
+ struct asic3 *asic;
+
+ asic = container_of(chip, struct asic3, gpio);
+ gpio_base = ASIC3_GPIO_TO_BASE(offset);
+
+ if (gpio_base > ASIC3_GPIO_D_BASE) {
+ dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
+ gpio_base, offset);
+ return -EINVAL;
+ }
spin_lock_irqsave(&asic->lock, flags);
- val |= (asic3_read_register(asic, base + function) & ~bits);
- asic3_write_register(asic, base + function, val);
+ out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
+
+ /* Input is 0, Output is 1 */
+ if (out)
+ out_reg |= mask;
+ else
+ out_reg &= ~mask;
+
+ asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
+
spin_unlock_irqrestore(&asic->lock, flags);
+
+ return 0;
+
+}
+
+static int asic3_gpio_direction_input(struct gpio_chip *chip,
+ unsigned offset)
+{
+ return asic3_gpio_direction(chip, offset, 0);
+}
+
+static int asic3_gpio_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
+{
+ return asic3_gpio_direction(chip, offset, 1);
}
-#define asic3_get_gpio_a(asic, fn) \
- asic3_get_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn)
-#define asic3_get_gpio_b(asic, fn) \
- asic3_get_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn)
-#define asic3_get_gpio_c(asic, fn) \
- asic3_get_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn)
-#define asic3_get_gpio_d(asic, fn) \
- asic3_get_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn)
-
-#define asic3_set_gpio_a(asic, fn, bits, val) \
- asic3_set_gpio(asic, ASIC3_GPIO_A_Base, ASIC3_GPIO_##fn, bits, val)
-#define asic3_set_gpio_b(asic, fn, bits, val) \
- asic3_set_gpio(asic, ASIC3_GPIO_B_Base, ASIC3_GPIO_##fn, bits, val)
-#define asic3_set_gpio_c(asic, fn, bits, val) \
- asic3_set_gpio(asic, ASIC3_GPIO_C_Base, ASIC3_GPIO_##fn, bits, val)
-#define asic3_set_gpio_d(asic, fn, bits, val) \
- asic3_set_gpio(asic, ASIC3_GPIO_D_Base, ASIC3_GPIO_##fn, bits, val)
-
-#define asic3_set_gpio_banks(asic, fn, bits, pdata, field) \
- do { \
- asic3_set_gpio_a((asic), fn, (bits), (pdata)->gpio_a.field); \
- asic3_set_gpio_b((asic), fn, (bits), (pdata)->gpio_b.field); \
- asic3_set_gpio_c((asic), fn, (bits), (pdata)->gpio_c.field); \
- asic3_set_gpio_d((asic), fn, (bits), (pdata)->gpio_d.field); \
- } while (0)
-
-int asic3_gpio_get_value(struct asic3 *asic, unsigned gpio)
+static int asic3_gpio_get(struct gpio_chip *chip,
+ unsigned offset)
{
- u32 mask = ASIC3_GPIO_bit(gpio);
-
- switch (gpio >> 4) {
- case ASIC3_GPIO_BANK_A:
- return asic3_get_gpio_a(asic, Status) & mask;
- case ASIC3_GPIO_BANK_B:
- return asic3_get_gpio_b(asic, Status) & mask;
- case ASIC3_GPIO_BANK_C:
- return asic3_get_gpio_c(asic, Status) & mask;
- case ASIC3_GPIO_BANK_D:
- return asic3_get_gpio_d(asic, Status) & mask;
- default:
- printk(KERN_ERR "%s: invalid GPIO value 0x%x",
- __func__, gpio);
+ unsigned int gpio_base;
+ u32 mask = ASIC3_GPIO_TO_MASK(offset);
+ struct asic3 *asic;
+
+ asic = container_of(chip, struct asic3, gpio);
+ gpio_base = ASIC3_GPIO_TO_BASE(offset);
+
+ if (gpio_base > ASIC3_GPIO_D_BASE) {
+ dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
+ gpio_base, offset);
return -EINVAL;
}
+
+ return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
}
-EXPORT_SYMBOL(asic3_gpio_get_value);
-void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val)
+static void asic3_gpio_set(struct gpio_chip *chip,
+ unsigned offset, int value)
{
- u32 mask = ASIC3_GPIO_bit(gpio);
- u32 bitval = 0;
- if (val)
- bitval = mask;
-
- switch (gpio >> 4) {
- case ASIC3_GPIO_BANK_A:
- asic3_set_gpio_a(asic, Out, mask, bitval);
- return;
- case ASIC3_GPIO_BANK_B:
- asic3_set_gpio_b(asic, Out, mask, bitval);
- return;
- case ASIC3_GPIO_BANK_C:
- asic3_set_gpio_c(asic, Out, mask, bitval);
- return;
- case ASIC3_GPIO_BANK_D:
- asic3_set_gpio_d(asic, Out, mask, bitval);
- return;
- default:
- printk(KERN_ERR "%s: invalid GPIO value 0x%x",
- __func__, gpio);
+ u32 mask, out_reg;
+ unsigned int gpio_base;
+ unsigned long flags;
+ struct asic3 *asic;
+
+ asic = container_of(chip, struct asic3, gpio);
+ gpio_base = ASIC3_GPIO_TO_BASE(offset);
+
+ if (gpio_base > ASIC3_GPIO_D_BASE) {
+ dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
+ gpio_base, offset);
return;
}
+
+ mask = ASIC3_GPIO_TO_MASK(offset);
+
+ spin_lock_irqsave(&asic->lock, flags);
+
+ out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
+
+ if (value)
+ out_reg |= mask;
+ else
+ out_reg &= ~mask;
+
+ asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
+
+ spin_unlock_irqrestore(&asic->lock, flags);
+
+ return;
}
-EXPORT_SYMBOL(asic3_gpio_set_value);
-static int asic3_gpio_probe(struct platform_device *pdev)
+static __init int asic3_gpio_probe(struct platform_device *pdev,
+ u16 *gpio_config, int num)
{
- struct asic3_platform_data *pdata = pdev->dev.platform_data;
struct asic3 *asic = platform_get_drvdata(pdev);
+ u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
+ u16 out_reg[ASIC3_NUM_GPIO_BANKS];
+ u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
+ int i;
+
+ memzero(alt_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
+ memzero(out_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
+ memzero(dir_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
+
+ /* Enable all GPIOs */
+ asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
+ asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
+ asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
+ asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
+
+ for (i = 0; i < num; i++) {
+ u8 alt, pin, dir, init, bank_num, bit_num;
+ u16 config = gpio_config[i];
+
+ pin = ASIC3_CONFIG_GPIO_PIN(config);
+ alt = ASIC3_CONFIG_GPIO_ALT(config);
+ dir = ASIC3_CONFIG_GPIO_DIR(config);
+ init = ASIC3_CONFIG_GPIO_INIT(config);
+
+ bank_num = ASIC3_GPIO_TO_BANK(pin);
+ bit_num = ASIC3_GPIO_TO_BIT(pin);
+
+ alt_reg[bank_num] |= (alt << bit_num);
+ out_reg[bank_num] |= (init << bit_num);
+ dir_reg[bank_num] |= (dir << bit_num);
+ }
- asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, Mask), 0xffff);
- asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, Mask), 0xffff);
- asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, Mask), 0xffff);
- asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, Mask), 0xffff);
-
- asic3_set_gpio_a(asic, SleepMask, 0xffff, 0xffff);
- asic3_set_gpio_b(asic, SleepMask, 0xffff, 0xffff);
- asic3_set_gpio_c(asic, SleepMask, 0xffff, 0xffff);
- asic3_set_gpio_d(asic, SleepMask, 0xffff, 0xffff);
-
- if (pdata) {
- asic3_set_gpio_banks(asic, Out, 0xffff, pdata, init);
- asic3_set_gpio_banks(asic, Direction, 0xffff, pdata, dir);
- asic3_set_gpio_banks(asic, SleepMask, 0xffff, pdata,
- sleep_mask);
- asic3_set_gpio_banks(asic, SleepOut, 0xffff, pdata, sleep_out);
- asic3_set_gpio_banks(asic, BattFaultOut, 0xffff, pdata,
- batt_fault_out);
- asic3_set_gpio_banks(asic, SleepConf, 0xffff, pdata,
- sleep_conf);
- asic3_set_gpio_banks(asic, AltFunction, 0xffff, pdata,
- alt_function);
+ for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
+ asic3_write_register(asic,
+ ASIC3_BANK_TO_BASE(i) +
+ ASIC3_GPIO_DIRECTION,
+ dir_reg[i]);
+ asic3_write_register(asic,
+ ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
+ out_reg[i]);
+ asic3_write_register(asic,
+ ASIC3_BANK_TO_BASE(i) +
+ ASIC3_GPIO_ALT_FUNCTION,
+ alt_reg[i]);
}
- return 0;
+ return gpiochip_add(&asic->gpio);
}
-static void asic3_gpio_remove(struct platform_device *pdev)
+static int asic3_gpio_remove(struct platform_device *pdev)
{
- return;
+ struct asic3 *asic = platform_get_drvdata(pdev);
+
+ return gpiochip_remove(&asic->gpio);
}
/* Core */
-static int asic3_probe(struct platform_device *pdev)
+static int __init asic3_probe(struct platform_device *pdev)
{
struct asic3_platform_data *pdata = pdev->dev.platform_data;
struct asic3 *asic;
struct resource *mem;
unsigned long clksel;
- int ret;
+ int ret = 0;
asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
- if (!asic)
+ if (asic == NULL) {
+ printk(KERN_ERR "kzalloc failed\n");
return -ENOMEM;
+ }
spin_lock_init(&asic->lock);
platform_set_drvdata(pdev, asic);
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!mem) {
ret = -ENOMEM;
- printk(KERN_ERR "asic3: no MEM resource\n");
- goto err_out_1;
+ dev_err(asic->dev, "no MEM resource\n");
+ goto out_free;
}
- asic->mapping = ioremap(mem->start, PAGE_SIZE);
+ map_size = mem->end - mem->start + 1;
+ asic->mapping = ioremap(mem->start, map_size);
if (!asic->mapping) {
ret = -ENOMEM;
- printk(KERN_ERR "asic3: couldn't ioremap\n");
- goto err_out_1;
+ dev_err(asic->dev, "Couldn't ioremap\n");
+ goto out_free;
}
asic->irq_base = pdata->irq_base;
- if (pdata && pdata->bus_shift)
- asic->bus_shift = 2 - pdata->bus_shift;
- else
- asic->bus_shift = 0;
+ /* calculate bus shift from mem resource */
+ asic->bus_shift = 2 - (map_size >> 12);
clksel = 0;
asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
ret = asic3_irq_probe(pdev);
if (ret < 0) {
- printk(KERN_ERR "asic3: couldn't probe IRQs\n");
- goto err_out_2;
+ dev_err(asic->dev, "Couldn't probe IRQs\n");
+ goto out_unmap;
}
- asic3_gpio_probe(pdev);
- if (pdata->children) {
- int i;
- for (i = 0; i < pdata->n_children; i++) {
- pdata->children[i]->dev.parent = &pdev->dev;
- platform_device_register(pdata->children[i]);
- }
+ asic->gpio.base = pdata->gpio_base;
+ asic->gpio.ngpio = ASIC3_NUM_GPIOS;
+ asic->gpio.get = asic3_gpio_get;
+ asic->gpio.set = asic3_gpio_set;
+ asic->gpio.direction_input = asic3_gpio_direction_input;
+ asic->gpio.direction_output = asic3_gpio_direction_output;
+
+ ret = asic3_gpio_probe(pdev,
+ pdata->gpio_config,
+ pdata->gpio_config_num);
+ if (ret < 0) {
+ dev_err(asic->dev, "GPIO probe failed\n");
+ goto out_irq;
}
- printk(KERN_INFO "ASIC3 Core driver\n");
+ dev_info(asic->dev, "ASIC3 Core driver\n");
return 0;
- err_out_2:
+ out_irq:
+ asic3_irq_remove(pdev);
+
+ out_unmap:
iounmap(asic->mapping);
- err_out_1:
+
+ out_free:
kfree(asic);
return ret;
static int asic3_remove(struct platform_device *pdev)
{
+ int ret;
struct asic3 *asic = platform_get_drvdata(pdev);
- asic3_gpio_remove(pdev);
+ ret = asic3_gpio_remove(pdev);
+ if (ret < 0)
+ return ret;
asic3_irq_remove(pdev);
asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
.driver = {
.name = "asic3",
},
- .probe = asic3_probe,
.remove = __devexit_p(asic3_remove),
.shutdown = asic3_shutdown,
};
static int __init asic3_init(void)
{
int retval = 0;
- retval = platform_driver_register(&asic3_device_driver);
+ retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
return retval;
}
* published by the Free Software Foundation.
*
* Copyright 2001 Compaq Computer Corporation.
- * Copyright 2007 OpendHand.
+ * Copyright 2007-2008 OpenedHand Ltd.
*/
#ifndef __ASIC3_H__
#include <linux/types.h>
-struct asic3 {
- void __iomem *mapping;
- unsigned int bus_shift;
- unsigned int irq_nr;
- unsigned int irq_base;
- spinlock_t lock;
- u16 irq_bothedge[4];
- struct device *dev;
-};
-
struct asic3_platform_data {
- struct {
- u32 dir;
- u32 init;
- u32 sleep_mask;
- u32 sleep_out;
- u32 batt_fault_out;
- u32 sleep_conf;
- u32 alt_function;
- } gpio_a, gpio_b, gpio_c, gpio_d;
-
- unsigned int bus_shift;
+ u16 *gpio_config;
+ unsigned int gpio_config_num;
unsigned int irq_base;
- struct platform_device **children;
- unsigned int n_children;
+ unsigned int gpio_base;
};
-int asic3_gpio_get_value(struct asic3 *asic, unsigned gpio);
-void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
-
#define ASIC3_NUM_GPIO_BANKS 4
#define ASIC3_GPIOS_PER_BANK 16
#define ASIC3_NUM_GPIOS 64
#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
+#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
+
#define ASIC3_GPIO_BANK_A 0
#define ASIC3_GPIO_BANK_B 1
#define ASIC3_GPIO_BANK_C 2
/* All offsets below are specified with this address bus shift */
#define ASIC3_DEFAULT_ADDR_SHIFT 2
-#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_Base + ASIC3_##base##_##reg)
+#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg)
#define ASIC3_GPIO_OFFSET(base, reg) \
- (ASIC3_GPIO_##base##_Base + ASIC3_GPIO_##reg)
-
-#define ASIC3_GPIO_A_Base 0x0000
-#define ASIC3_GPIO_B_Base 0x0100
-#define ASIC3_GPIO_C_Base 0x0200
-#define ASIC3_GPIO_D_Base 0x0300
-
-#define ASIC3_GPIO_Mask 0x00 /* R/W 0:don't mask */
-#define ASIC3_GPIO_Direction 0x04 /* R/W 0:input */
-#define ASIC3_GPIO_Out 0x08 /* R/W 0:output low */
-#define ASIC3_GPIO_TriggerType 0x0c /* R/W 0:level */
-#define ASIC3_GPIO_EdgeTrigger 0x10 /* R/W 0:falling */
-#define ASIC3_GPIO_LevelTrigger 0x14 /* R/W 0:low level detect */
-#define ASIC3_GPIO_SleepMask 0x18 /* R/W 0:don't mask in sleep mode */
-#define ASIC3_GPIO_SleepOut 0x1c /* R/W level 0:low in sleep mode */
-#define ASIC3_GPIO_BattFaultOut 0x20 /* R/W level 0:low in batt_fault */
-#define ASIC3_GPIO_IntStatus 0x24 /* R/W 0:none, 1:detect */
-#define ASIC3_GPIO_AltFunction 0x28 /* R/W 1:LED register control */
-#define ASIC3_GPIO_SleepConf 0x2c /*
+ (ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg)
+
+#define ASIC3_GPIO_A_BASE 0x0000
+#define ASIC3_GPIO_B_BASE 0x0100
+#define ASIC3_GPIO_C_BASE 0x0200
+#define ASIC3_GPIO_D_BASE 0x0300
+
+#define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
+#define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \
+ (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
+#define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
+#define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100))
+#define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100))
+
+#define ASIC3_GPIO_MASK 0x00 /* R/W 0:don't mask */
+#define ASIC3_GPIO_DIRECTION 0x04 /* R/W 0:input */
+#define ASIC3_GPIO_OUT 0x08 /* R/W 0:output low */
+#define ASIC3_GPIO_TRIGGER_TYPE 0x0c /* R/W 0:level */
+#define ASIC3_GPIO_EDGE_TRIGGER 0x10 /* R/W 0:falling */
+#define ASIC3_GPIO_LEVEL_TRIGGER 0x14 /* R/W 0:low level detect */
+#define ASIC3_GPIO_SLEEP_MASK 0x18 /* R/W 0:don't mask in sleep mode */
+#define ASIC3_GPIO_SLEEP_OUT 0x1c /* R/W level 0:low in sleep mode */
+#define ASIC3_GPIO_BAT_FAULT_OUT 0x20 /* R/W level 0:low in batt_fault */
+#define ASIC3_GPIO_INT_STATUS 0x24 /* R/W 0:none, 1:detect */
+#define ASIC3_GPIO_ALT_FUNCTION 0x28 /* R/W 1:LED register control */
+#define ASIC3_GPIO_SLEEP_CONF 0x2c /*
* R/W bit 1: autosleep
* 0: disable gposlpout in normal mode,
* enable gposlpout in sleep mode.
*/
-#define ASIC3_GPIO_Status 0x30 /* R Pin status */
+#define ASIC3_GPIO_STATUS 0x30 /* R Pin status */
+
+/*
+ * ASIC3 GPIO config
+ *
+ * Bits 0..6 gpio number
+ * Bits 7..13 Alternate function
+ * Bit 14 Direction
+ * Bit 15 Initial value
+ *
+ */
+#define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f)
+#define ASIC3_CONFIG_GPIO_ALT(config) (((config) & (0x7f << 7)) >> 7)
+#define ASIC3_CONFIG_GPIO_DIR(config) ((config & (1 << 14)) >> 14)
+#define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15)
+#define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \
+ | (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \
+ | (((init) & 0x1) << 15))
+#define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \
+ ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init))
+#define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \
+ ASIC3_CONFIG_GPIO((gpio), 0, 1, (init))
+
+/*
+ * Alternate functions
+ */
+#define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0)
+#define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0)
+#define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0)
+#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 1, 0)
+#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 1, 0)
+#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 1, 0)
+#define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0)
+#define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0)
+#define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0)
+#define ASIC3_GPIOC5_SPI_CLK ASIC3_CONFIG_GPIO(37, 1, 1, 0)
+#define ASIC3_GPIOC5_nCIOW ASIC3_CONFIG_GPIO(37, 1, 1, 0)
+#define ASIC3_GPIOC6_nCIOR ASIC3_CONFIG_GPIO(38, 1, 1, 0)
+#define ASIC3_GPIOC7_nPCE_1 ASIC3_CONFIG_GPIO(39, 1, 0, 0)
+#define ASIC3_GPIOC8_nPCE_2 ASIC3_CONFIG_GPIO(40, 1, 0, 0)
+#define ASIC3_GPIOC9_nPOE ASIC3_CONFIG_GPIO(41, 1, 0, 0)
+#define ASIC3_GPIOC10_nPWE ASIC3_CONFIG_GPIO(42, 1, 0, 0)
+#define ASIC3_GPIOC11_PSKTSEL ASIC3_CONFIG_GPIO(43, 1, 0, 0)
+#define ASIC3_GPIOC12_nPREG ASIC3_CONFIG_GPIO(44, 1, 0, 0)
+#define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0)
+#define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0)
+#define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0)
+#define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0)
+#define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0)
+#define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0)
+
#define ASIC3_SPI_Base 0x0400
#define ASIC3_SPI_Control 0x0000
#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
-#define ASIC3_CLOCK_Base 0x0A00
+#define ASIC3_CLOCK_BASE 0x0A00
#define ASIC3_CLOCK_CDEX 0x00
#define ASIC3_CLOCK_SEL 0x04
#define CLOCK_SEL_CX (1 << 2)
-#define ASIC3_INTR_Base 0x0B00
+#define ASIC3_INTR_BASE 0x0B00
-#define ASIC3_INTR_IntMask 0x00 /* Interrupt mask control */
-#define ASIC3_INTR_PIntStat 0x04 /* Peripheral interrupt status */
-#define ASIC3_INTR_IntCPS 0x08 /* Interrupt timer clock pre-scale */
-#define ASIC3_INTR_IntTBS 0x0c /* Interrupt timer set */
+#define ASIC3_INTR_INT_MASK 0x00 /* Interrupt mask control */
+#define ASIC3_INTR_P_INT_STAT 0x04 /* Peripheral interrupt status */
+#define ASIC3_INTR_INT_CPS 0x08 /* Interrupt timer clock pre-scale */
+#define ASIC3_INTR_INT_TBS 0x0c /* Interrupt timer set */
#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */
#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */
#define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */
/*********************************************
- * The Onewire interface registers
- *
- * OWM_CMD
- * OWM_DAT
- * OWM_INTR
- * OWM_INTEN
- * OWM_CLKDIV
+ * The Onewire interface (DS1WM) is handled
+ * by the ds1wm driver.
*
*********************************************/
-#define ASIC3_OWM_Base 0xC00
-
-#define ASIC3_OWM_CMD 0x00
-#define ASIC3_OWM_DAT 0x04
-#define ASIC3_OWM_INTR 0x08
-#define ASIC3_OWM_INTEN 0x0C
-#define ASIC3_OWM_CLKDIV 0x10
-
-#define ASIC3_OWM_CMD_ONEWR (1 << 0)
-#define ASIC3_OWM_CMD_SRA (1 << 1)
-#define ASIC3_OWM_CMD_DQO (1 << 2)
-#define ASIC3_OWM_CMD_DQI (1 << 3)
-
-#define ASIC3_OWM_INTR_PD (1 << 0)
-#define ASIC3_OWM_INTR_PDR (1 << 1)
-#define ASIC3_OWM_INTR_TBE (1 << 2)
-#define ASIC3_OWM_INTR_TEMP (1 << 3)
-#define ASIC3_OWM_INTR_RBF (1 << 4)
-
-#define ASIC3_OWM_INTEN_EPD (1 << 0)
-#define ASIC3_OWM_INTEN_IAS (1 << 1)
-#define ASIC3_OWM_INTEN_ETBE (1 << 2)
-#define ASIC3_OWM_INTEN_ETMT (1 << 3)
-#define ASIC3_OWM_INTEN_ERBF (1 << 4)
-
-#define ASIC3_OWM_CLKDIV_PRE (3 << 0) /* two bits wide at bit 0 */
-#define ASIC3_OWM_CLKDIV_DIV (7 << 2) /* 3 bits wide at bit 2 */
-
+#define ASIC3_OWM_BASE 0xC00
/*****************************************************************************
* The SD configuration registers are at a completely different location
#define ASIC3_SDIO_CTRL_LEDCtrl 0x7C
#define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0
-#define ASIC3_MAP_SIZE 0x2000
+#define ASIC3_MAP_SIZE_32BIT 0x2000
+#define ASIC3_MAP_SIZE_16BIT 0x1000
#endif /* __ASIC3_H__ */
git.openpandora.org / pandora-kernel.git / commitdiff