MIPS: OCTEON: More OCTEONIII support

Read clock rate from the correct CSR. Don't clear COP0_DCACHE for OCTEONIII.

Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8945/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --cc arch/mips/cavium-octeon/csrc-octeon.c
Simple merge

diff --cc arch/mips/cavium-octeon/setup.c
Simple merge

diff --cc arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
Simple merge

diff --cc arch/mips/include/asm/octeon/cvmx-rst-defs.h
Simple merge