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ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi
authorStephen Warren <swarren@nvidia.com>
Wed, 23 Jan 2013 16:43:49 +0000 (09:43 -0700)
committerStephen Warren <swarren@nvidia.com>
Mon, 28 Jan 2013 18:24:09 +0000 (11:24 -0700)
No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

No differences found
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