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ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi
authorLucas Stach <dev@lynxeye.de>
Tue, 22 Jan 2013 21:46:07 +0000 (22:46 +0100)
committerStephen Warren <swarren@nvidia.com>
Mon, 28 Jan 2013 18:24:09 +0000 (11:24 -0700)
No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

No differences found
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