x86: prevent C-states hang on AMD C1E enabled machines

Impact: System hang when AMD C1E machines switch into C2/C3

AMD C1E enabled systems do not work with normal ACPI C-states
even if the BIOS is advertising them. Limit the C-states to
C1 for the ACPI processor idle code.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 2e22471..d8c2a29 100644 (file)
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -272,6 +272,7 @@ static void c1e_idle(void)
                        c1e_detected = 1;
                        mark_tsc_unstable("TSC halt in C1E");
                        printk(KERN_INFO "System has C1E enabled\n");
+                       set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
                }
        }
 

diff --git a/include/asm-x86/acpi.h b/include/asm-x86/acpi.h
index 635d764..35d1743 100644 (file)
--- a/include/asm-x86/acpi.h
+++ b/include/asm-x86/acpi.h
@@ -140,6 +140,8 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
            boot_cpu_data.x86_model <= 0x05 &&
            boot_cpu_data.x86_mask < 0x0A)
                return 1;
+       else if (boot_cpu_has(X86_FEATURE_AMDC1E))
+               return 1;
        else
                return max_cstate;
 }

diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 9489283..cfcfb0a 100644 (file)
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -81,6 +81,7 @@
 #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
 #define X86_FEATURE_11AP       (3*32+19) /* Bad local APIC aka 11AP */
 #define X86_FEATURE_NOPL       (3*32+20) /* The NOPL (0F 1F) instructions */
+#define X86_FEATURE_AMDC1E     (3*32+21) /* AMD C1E detected */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3       (4*32+ 0) /* Streaming SIMD Extensions-3 */