* handle.
*/
mask = 0;
- if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
+ if (__cpu_fifo_underrun_reporting_enabled(dev_priv, pipe))
mask |= PIPE_FIFO_UNDERRUN_STATUS;
switch (pipe) {
i9xx_pipe_crc_irq_handler(dev, pipe);
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
- intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
+ intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
+ false))
DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
}
DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
if (pch_iir & SDE_TRANSA_FIFO_UNDER)
- if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
+ if (intel_set_pch_fifo_underrun_reporting(dev_priv,
+ TRANSCODER_A,
false))
DRM_ERROR("PCH transcoder A FIFO underrun\n");
if (pch_iir & SDE_TRANSB_FIFO_UNDER)
- if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
+ if (intel_set_pch_fifo_underrun_reporting(dev_priv,
+ TRANSCODER_B,
false))
DRM_ERROR("PCH transcoder B FIFO underrun\n");
}
for_each_pipe(dev_priv, pipe) {
if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
- if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
+ if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
false))
DRM_ERROR("Pipe %c FIFO underrun\n",
pipe_name(pipe));
DRM_ERROR("PCH poison interrupt\n");
if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
- if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
+ if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
false))
DRM_ERROR("PCH transcoder A FIFO underrun\n");
if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
- if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
+ if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_B,
false))
DRM_ERROR("PCH transcoder B FIFO underrun\n");
if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
- if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
+ if (intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_C,
false))
DRM_ERROR("PCH transcoder C FIFO underrun\n");
intel_check_page_flip(dev, pipe);
if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
- if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
+ if (intel_set_cpu_fifo_underrun_reporting(dev_priv,
+ pipe,
+ false))
DRM_ERROR("Pipe %c FIFO underrun\n",
pipe_name(pipe));
hsw_pipe_crc_irq_handler(dev, pipe);
if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
- if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
+ if (intel_set_cpu_fifo_underrun_reporting(dev_priv,
+ pipe,
false))
DRM_ERROR("Pipe %c FIFO underrun\n",
pipe_name(pipe));
i9xx_pipe_crc_irq_handler(dev, pipe);
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
- intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
+ intel_set_cpu_fifo_underrun_reporting(dev_priv,
+ pipe, false))
DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
}
i9xx_pipe_crc_irq_handler(dev, pipe);
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
- intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
+ intel_set_cpu_fifo_underrun_reporting(dev_priv,
+ pipe, false))
DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
}
i9xx_pipe_crc_irq_handler(dev, pipe);
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
- intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
+ intel_set_cpu_fifo_underrun_reporting(dev_priv,
+ pipe, false))
DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
}