firmware: scmi: Drop mmu_set_region_dcache_behaviour() misuse

MMU region cache behavior configuration for SCMI/SMT mailboxes is
platform specific. Even on ARM systems, the mailbox memory may not
even be located in any cacheable MMU region and may instead reside
in some SRAM. Remove this non-generic cache behavior configuration
code from generic code path.

It is unlikely that any platform is affected by this change if it
did configure its MMU regions correctly on start up. Platforms
which might be affected are i.MX94/95 and STM32MP.

Fixes: 240720e9052f ("firmware: scmi: mailbox/smt agent device")
Fixes: 2a3f161c8b16 ("scmi: correctly configure MMU for SCMI buffer")
Fixes: b2ae10970d40 ("firmware: scmi: use PAGE_SIZE alignment for ARM64")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Tested-by: Alice Guo <alice.guo@nxp.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c
index 2378715..cd1c080 100644 (file)
--- a/drivers/firmware/scmi/smt.c
+++ b/drivers/firmware/scmi/smt.c
@@ -61,20 +61,6 @@ int scmi_dt_get_smt_buffer(struct udevice *dev, struct scmi_smt *smt)
        if (device_is_compatible(dev, "arm,scmi") && ofnode_has_property(dev_ofnode(dev), "mboxes"))
                scmi_smt_enable_intr(smt, true);
 
-#ifdef CONFIG_ARM
-       if (dcache_status()) {
-               u32 align_size;
-
-               if (IS_ENABLED(CONFIG_ARM64))
-                       align_size = PAGE_SIZE;
-               else
-                       align_size = MMU_SECTION_SIZE;
-
-               mmu_set_region_dcache_behaviour(ALIGN_DOWN((uintptr_t)smt->buf, align_size),
-                                               ALIGN(smt->size, align_size), DCACHE_OFF);
-       }
-#endif
-
        return 0;
 }