rockchip: rk356x-u-boot: Add bootph-all to common pinctrl nodes

Add bootph-all prop to common pinctrl nodes for eMMC, FSPI, SD-card and
UART2 that are typically used by multiple boards. Unreferenced nodes are
removed from the SPL device tree during a normal build.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
index 57b7715..c925439 100644 (file)
--- a/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-radxa-cm3-io-u-boot.dtsi
@@ -11,67 +11,11 @@
        };
 };
 
-&emmc_bus8 {
-       bootph-all;
-};
-
-&emmc_clk {
-       bootph-all;
-};
-
-&emmc_cmd {
-       bootph-all;
-};
-
-&emmc_datastrobe {
-       bootph-all;
-};
-
-&pinctrl {
-       bootph-all;
-};
-
-&pcfg_pull_none {
-       bootph-all;
-};
-
-&pcfg_pull_up_drv_level_2 {
-       bootph-all;
-};
-
-&pcfg_pull_up {
-       bootph-all;
-};
-
-&sdmmc0_bus4 {
-       bootph-all;
-};
-
-&sdmmc0_clk {
-       bootph-all;
-};
-
-&sdmmc0_cmd {
-       bootph-all;
-};
-
-&sdmmc0_det {
-       bootph-all;
-};
-
-&sdmmc0_pwren {
-       bootph-all;
-};
-
 &sdhci {
        cap-mmc-highspeed;
        mmc-ddr-1_8v;
 };
 
-&uart2m0_xfer {
-       bootph-all;
-};
-
 &uart2 {
        clock-frequency = <24000000>;
        bootph-all;

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index a6cee56..45e06a9 100644 (file)
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -16,26 +16,6 @@
        };
 };
 
-&emmc_bus8 {
-       bootph-all;
-};
-
-&emmc_clk {
-       bootph-all;
-};
-
-&emmc_cmd {
-       bootph-all;
-};
-
-&emmc_datastrobe {
-       bootph-all;
-};
-
-&fspi_pins {
-       bootph-all;
-};
-
 &pcie2x1 {
        pinctrl-0 = <&pcie20m1_pins &pcie_reset_h>;
 };
@@ -45,8 +25,6 @@
 };
 
 &pinctrl {
-       bootph-all;
-
        pcie {
                pcie3x2_reset_h: pcie3x2-reset-h {
                        rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -54,34 +32,6 @@
        };
 };
 
-&pcfg_pull_none {
-       bootph-all;
-};
-
-&pcfg_pull_up_drv_level_2 {
-       bootph-all;
-};
-
-&pcfg_pull_up {
-       bootph-all;
-};
-
-&sdmmc0_bus4 {
-       bootph-all;
-};
-
-&sdmmc0_clk {
-       bootph-all;
-};
-
-&sdmmc0_cmd {
-       bootph-all;
-};
-
-&sdmmc0_det {
-       bootph-all;
-};
-
 &sdhci {
        cap-mmc-highspeed;
        mmc-ddr-1_8v;
@@ -115,10 +65,6 @@
        status = "disabled";
 };
 
-&uart2m0_xfer {
-       bootph-all;
-};
-
 &uart2 {
        clock-frequency = <24000000>;
        bootph-all;

diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi
index c340c2b..89c0d83 100644 (file)
--- a/arch/arm/dts/rk356x-u-boot.dtsi
+++ b/arch/arm/dts/rk356x-u-boot.dtsi
@@ -59,6 +59,70 @@
        status = "okay";
 };
 
+&pinctrl {
+       bootph-all;
+};
+
+&pcfg_pull_none {
+       bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+       bootph-all;
+};
+
+&pcfg_pull_up {
+       bootph-all;
+};
+
+&emmc_bus8 {
+       bootph-all;
+};
+
+&emmc_clk {
+       bootph-all;
+};
+
+&emmc_cmd {
+       bootph-all;
+};
+
+&emmc_datastrobe {
+       bootph-all;
+};
+
+&emmc_rstnout {
+       bootph-all;
+};
+
+&fspi_pins {
+       bootph-all;
+};
+
+&sdmmc0_bus4 {
+       bootph-all;
+};
+
+&sdmmc0_clk {
+       bootph-all;
+};
+
+&sdmmc0_cmd {
+       bootph-all;
+};
+
+&sdmmc0_det {
+       bootph-all;
+};
+
+&sdmmc0_pwren {
+       bootph-all;
+};
+
+&uart2m0_xfer {
+       bootph-all;
+};
+
 &sdhci {
        bootph-pre-ram;
        status = "okay";