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[MIPS] SB1: Fix interrupt disable hazard.
authorRalf Baechle <ralf@linux-mips.org>
Mon, 13 Mar 2006 16:16:29 +0000 (16:16 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Sat, 18 Mar 2006 16:59:26 +0000 (16:59 +0000)
The SB1 core has a three cycle interrupt disable hazard but we were
wrongly treating it as fully interlocked.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

No differences found
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