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arm64: fix typo in I-cache policy detection
authorArd Biesheuvel <ard.biesheuvel@linaro.org>
Tue, 5 Aug 2014 09:25:55 +0000 (10:25 +0100)
committerWill Deacon <will.deacon@arm.com>
Mon, 18 Aug 2014 18:47:03 +0000 (19:47 +0100)
This removes an unfortunately placed semi-colon resulting in all instruction
caches being classified as AIVIVT.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

No differences found
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