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AT91: pm: make sure that r0 is 0 when dealing with cache operations
author
Nicolas Ferre
<nicolas.ferre@atmel.com>
Fri, 22 Oct 2010 16:55:39 +0000
(18:55 +0200)
committer
Nicolas Ferre
<nicolas.ferre@atmel.com>
Tue, 26 Oct 2010 09:32:48 +0000
(11:32 +0200)
When using CP15 cache operations (c7), we make sure that Rd (r0)
is actually 0 as ARM 926 TRM is saying.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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git.openpandora.org / pandora-kernel.git / commitdiff