drm/i915: Set i9xx sdvo clock limits according to specifications
authorPatrik Jakobsson <patrik.r.jakobsson@gmail.com>
Wed, 13 Feb 2013 21:20:22 +0000 (22:20 +0100)
committerBen Hutchings <ben@decadent.org.uk>
Wed, 6 Mar 2013 03:24:07 +0000 (03:24 +0000)
commit 4f7dfb6788dd022446847fbbfbe45e13bedb5be2 upstream.

The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56359
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>

No differences found