drm/radeon: fix bank information in tiling config
authorAlex Deucher <alexander.deucher@amd.com>
Thu, 31 May 2012 22:53:36 +0000 (18:53 -0400)
committerBen Hutchings <ben@decadent.org.uk>
Sun, 10 Jun 2012 13:41:53 +0000 (14:41 +0100)
commit 29d654067a98c1cb8874c774e5fd799a038af8a6 upstream.

While there are cards with more than 8 mem banks, the max
number of banks from a tiling perspective is 8, so cap
the tiling config at 8 banks.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=43448

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
[bwh: Backported to 3.2: fix up context and indentation for missing
 IGP condition in ni.c]
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>

No differences found