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ARM: perf: don't pretend to support counting of L1I writes
authorWill Deacon <will.deacon@arm.com>
Wed, 16 Jan 2013 12:01:59 +0000 (12:01 +0000)
committerGrazvydas Ignotas <notasas@gmail.com>
Thu, 4 Jul 2013 22:54:15 +0000 (01:54 +0300)
ARM has a harvard cache architecture and cannot write directly to the
I-side.

This patch removes the L1I write events from the cache map (which
previously returned *read* events in many cases).

Reported-by: Mike Williams <michael.williams@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Conflicts:

arch/arm/kernel/perf_event_v7.c


No differences found
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