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clk: samsung: exynos7: add gate clock for DMA block
authorPadmavathi Venna <padma.v@samsung.com>
Tue, 13 Jan 2015 11:27:40 +0000 (16:57 +0530)
committerSylwester Nawrocki <s.nawrocki@samsung.com>
Thu, 15 Jan 2015 14:11:40 +0000 (15:11 +0100)
Add support for PDMA0 and PDMA1 gate clks.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

No differences found
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