perf/x86/intel: Drain the PEBS buffer during context switches

Flush the PEBS buffer during context switches if PEBS interrupt threshold
is larger than one. This allows perf to supply TID for sample outputs.

Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
Signed-off-by: Kan Liang <kan.liang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: acme@infradead.org
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1430940834-8964-6-git-send-email-kan.liang@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>

diff --cc arch/x86/kernel/cpu/perf_event.h
Simple merge

diff --cc arch/x86/kernel/cpu/perf_event_intel.c
Simple merge

diff --cc arch/x86/kernel/cpu/perf_event_intel_ds.c
Simple merge

diff --cc arch/x86/kernel/cpu/perf_event_intel_lbr.c
Simple merge