+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Pinctrl driver for Rockchip 3036 SoCs
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3036.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <dm/pinctrl.h>
-
-/* GRF_GPIO0A_IOMUX */
-enum {
- GPIO0A3_SHIFT = 6,
- GPIO0A3_MASK = 1 << GPIO0A3_SHIFT,
- GPIO0A3_GPIO = 0,
- GPIO0A3_I2C1_SDA,
-
- GPIO0A2_SHIFT = 4,
- GPIO0A2_MASK = 1 << GPIO0A2_SHIFT,
- GPIO0A2_GPIO = 0,
- GPIO0A2_I2C1_SCL,
-
- GPIO0A1_SHIFT = 2,
- GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
- GPIO0A1_GPIO = 0,
- GPIO0A1_I2C0_SDA,
- GPIO0A1_PWM2,
-
- GPIO0A0_SHIFT = 0,
- GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
- GPIO0A0_GPIO = 0,
- GPIO0A0_I2C0_SCL,
- GPIO0A0_PWM1,
-};
-
-/* GRF_GPIO0B_IOMUX */
-enum {
- GPIO0B6_SHIFT = 12,
- GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
- GPIO0B6_GPIO = 0,
- GPIO0B6_MMC1_D3,
- GPIO0B6_I2S1_SCLK,
-
- GPIO0B5_SHIFT = 10,
- GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
- GPIO0B5_GPIO = 0,
- GPIO0B5_MMC1_D2,
- GPIO0B5_I2S1_SDI,
-
- GPIO0B4_SHIFT = 8,
- GPIO0B4_MASK = 3 << GPIO0B4_SHIFT,
- GPIO0B4_GPIO = 0,
- GPIO0B4_MMC1_D1,
- GPIO0B4_I2S1_LRCKTX,
-
- GPIO0B3_SHIFT = 6,
- GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
- GPIO0B3_GPIO = 0,
- GPIO0B3_MMC1_D0,
- GPIO0B3_I2S1_LRCKRX,
-
- GPIO0B1_SHIFT = 2,
- GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
- GPIO0B1_GPIO = 0,
- GPIO0B1_MMC1_CLKOUT,
- GPIO0B1_I2S1_MCLK,
-
- GPIO0B0_SHIFT = 0,
- GPIO0B0_MASK = 3,
- GPIO0B0_GPIO = 0,
- GPIO0B0_MMC1_CMD,
- GPIO0B0_I2S1_SDO,
-};
-
-/* GRF_GPIO0C_IOMUX */
-enum {
- GPIO0C4_SHIFT = 8,
- GPIO0C4_MASK = 1 << GPIO0C4_SHIFT,
- GPIO0C4_GPIO = 0,
- GPIO0C4_DRIVE_VBUS,
-
- GPIO0C3_SHIFT = 6,
- GPIO0C3_MASK = 1 << GPIO0C3_SHIFT,
- GPIO0C3_GPIO = 0,
- GPIO0C3_UART0_CTSN,
-
- GPIO0C2_SHIFT = 4,
- GPIO0C2_MASK = 1 << GPIO0C2_SHIFT,
- GPIO0C2_GPIO = 0,
- GPIO0C2_UART0_RTSN,
-
- GPIO0C1_SHIFT = 2,
- GPIO0C1_MASK = 1 << GPIO0C1_SHIFT,
- GPIO0C1_GPIO = 0,
- GPIO0C1_UART0_SIN,
-
-
- GPIO0C0_SHIFT = 0,
- GPIO0C0_MASK = 1 << GPIO0C0_SHIFT,
- GPIO0C0_GPIO = 0,
- GPIO0C0_UART0_SOUT,
-};
-
-/* GRF_GPIO0D_IOMUX */
-enum {
- GPIO0D4_SHIFT = 8,
- GPIO0D4_MASK = 1 << GPIO0D4_SHIFT,
- GPIO0D4_GPIO = 0,
- GPIO0D4_SPDIF,
-
- GPIO0D3_SHIFT = 6,
- GPIO0D3_MASK = 1 << GPIO0D3_SHIFT,
- GPIO0D3_GPIO = 0,
- GPIO0D3_PWM3,
-
- GPIO0D2_SHIFT = 4,
- GPIO0D2_MASK = 1 << GPIO0D2_SHIFT,
- GPIO0D2_GPIO = 0,
- GPIO0D2_PWM0,
-};
-
-/* GRF_GPIO1A_IOMUX */
-enum {
- GPIO1A5_SHIFT = 10,
- GPIO1A5_MASK = 1 << GPIO1A5_SHIFT,
- GPIO1A5_GPIO = 0,
- GPIO1A5_I2S_SDI,
-
- GPIO1A4_SHIFT = 8,
- GPIO1A4_MASK = 1 << GPIO1A4_SHIFT,
- GPIO1A4_GPIO = 0,
- GPIO1A4_I2S_SD0,
-
- GPIO1A3_SHIFT = 6,
- GPIO1A3_MASK = 1 << GPIO1A3_SHIFT,
- GPIO1A3_GPIO = 0,
- GPIO1A3_I2S_LRCKTX,
-
- GPIO1A2_SHIFT = 4,
- GPIO1A2_MASK = 3 << GPIO1A2_SHIFT,
- GPIO1A2_GPIO = 0,
- GPIO1A2_I2S_LRCKRX,
- GPIO1A2_PWM1_0,
-
- GPIO1A1_SHIFT = 2,
- GPIO1A1_MASK = 1 << GPIO1A1_SHIFT,
- GPIO1A1_GPIO = 0,
- GPIO1A1_I2S_SCLK,
-
- GPIO1A0_SHIFT = 0,
- GPIO1A0_MASK = 1 << GPIO1A0_SHIFT,
- GPIO1A0_GPIO = 0,
- GPIO1A0_I2S_MCLK,
-
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK = 1 << GPIO1B7_SHIFT,
- GPIO1B7_GPIO = 0,
- GPIO1B7_MMC0_CMD,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK = 1 << GPIO1B3_SHIFT,
- GPIO1B3_GPIO = 0,
- GPIO1B3_HDMI_HPD,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK = 1 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO = 0,
- GPIO1B2_HDMI_SCL,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 1 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO = 0,
- GPIO1B1_HDMI_SDA,
-
- GPIO1B0_SHIFT = 0,
- GPIO1B0_MASK = 1 << GPIO1B0_SHIFT,
- GPIO1B0_GPIO = 0,
- GPIO1B0_HDMI_CEC,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
- GPIO1C5_GPIO = 0,
- GPIO1C5_MMC0_D3,
- GPIO1C5_JTAG_TMS,
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
- GPIO1C4_GPIO = 0,
- GPIO1C4_MMC0_D2,
- GPIO1C4_JTAG_TCK,
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
- GPIO1C3_GPIO = 0,
- GPIO1C3_MMC0_D1,
- GPIO1C3_UART2_SOUT,
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
- GPIO1C2_GPIO = 0,
- GPIO1C2_MMC0_D0,
- GPIO1C2_UART2_SIN,
-
- GPIO1C1_SHIFT = 2,
- GPIO1C1_MASK = 1 << GPIO1C1_SHIFT,
- GPIO1C1_GPIO = 0,
- GPIO1C1_MMC0_DETN,
-
- GPIO1C0_SHIFT = 0,
- GPIO1C0_MASK = 1 << GPIO1C0_SHIFT,
- GPIO1C0_GPIO = 0,
- GPIO1C0_MMC0_CLKOUT,
-};
-
-/* GRF_GPIO1D_IOMUX */
-enum {
- GPIO1D7_SHIFT = 14,
- GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
- GPIO1D7_GPIO = 0,
- GPIO1D7_NAND_D7,
- GPIO1D7_EMMC_D7,
- GPIO1D7_SPI_CSN1,
-
- GPIO1D6_SHIFT = 12,
- GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
- GPIO1D6_GPIO = 0,
- GPIO1D6_NAND_D6,
- GPIO1D6_EMMC_D6,
- GPIO1D6_SPI_CSN0,
-
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
- GPIO1D5_GPIO = 0,
- GPIO1D5_NAND_D5,
- GPIO1D5_EMMC_D5,
- GPIO1D5_SPI_TXD,
-
- GPIO1D4_SHIFT = 8,
- GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
- GPIO1D4_GPIO = 0,
- GPIO1D4_NAND_D4,
- GPIO1D4_EMMC_D4,
- GPIO1D4_SPI_RXD,
-
- GPIO1D3_SHIFT = 6,
- GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
- GPIO1D3_GPIO = 0,
- GPIO1D3_NAND_D3,
- GPIO1D3_EMMC_D3,
- GPIO1D3_SFC_SIO3,
-
- GPIO1D2_SHIFT = 4,
- GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
- GPIO1D2_GPIO = 0,
- GPIO1D2_NAND_D2,
- GPIO1D2_EMMC_D2,
- GPIO1D2_SFC_SIO2,
-
- GPIO1D1_SHIFT = 2,
- GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
- GPIO1D1_GPIO = 0,
- GPIO1D1_NAND_D1,
- GPIO1D1_EMMC_D1,
- GPIO1D1_SFC_SIO1,
-
- GPIO1D0_SHIFT = 0,
- GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
- GPIO1D0_GPIO = 0,
- GPIO1D0_NAND_D0,
- GPIO1D0_EMMC_D0,
- GPIO1D0_SFC_SIO0,
-};
-
-/* GRF_GPIO2A_IOMUX */
-enum {
- GPIO2A7_SHIFT = 14,
- GPIO2A7_MASK = 1 << GPIO2A7_SHIFT,
- GPIO2A7_GPIO = 0,
- GPIO2A7_TESTCLK_OUT,
-
- GPIO2A6_SHIFT = 12,
- GPIO2A6_MASK = 1 << GPIO2A6_SHIFT,
- GPIO2A6_GPIO = 0,
- GPIO2A6_NAND_CS0,
-
- GPIO2A4_SHIFT = 8,
- GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
- GPIO2A4_GPIO = 0,
- GPIO2A4_NAND_RDY,
- GPIO2A4_EMMC_CMD,
- GPIO2A3_SFC_CLK,
-
- GPIO2A3_SHIFT = 6,
- GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
- GPIO2A3_GPIO = 0,
- GPIO2A3_NAND_RDN,
- GPIO2A4_SFC_CSN1,
-
- GPIO2A2_SHIFT = 4,
- GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
- GPIO2A2_GPIO = 0,
- GPIO2A2_NAND_WRN,
- GPIO2A4_SFC_CSN0,
-
- GPIO2A1_SHIFT = 2,
- GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
- GPIO2A1_GPIO = 0,
- GPIO2A1_NAND_CLE,
- GPIO2A1_EMMC_CLKOUT,
-
- GPIO2A0_SHIFT = 0,
- GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
- GPIO2A0_GPIO = 0,
- GPIO2A0_NAND_ALE,
- GPIO2A0_SPI_CLK,
-};
-
-/* GRF_GPIO2B_IOMUX */
-enum {
- GPIO2B7_SHIFT = 14,
- GPIO2B7_MASK = 1 << GPIO2B7_SHIFT,
- GPIO2B7_GPIO = 0,
- GPIO2B7_MAC_RXER,
-
- GPIO2B6_SHIFT = 12,
- GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
- GPIO2B6_GPIO = 0,
- GPIO2B6_MAC_CLKOUT,
- GPIO2B6_MAC_CLKIN,
-
- GPIO2B5_SHIFT = 10,
- GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
- GPIO2B5_GPIO = 0,
- GPIO2B5_MAC_TXEN,
-
- GPIO2B4_SHIFT = 8,
- GPIO2B4_MASK = 1 << GPIO2B4_SHIFT,
- GPIO2B4_GPIO = 0,
- GPIO2B4_MAC_MDIO,
-
- GPIO2B2_SHIFT = 4,
- GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
- GPIO2B2_GPIO = 0,
- GPIO2B2_MAC_CRS,
-};
-
-/* GRF_GPIO2C_IOMUX */
-enum {
- GPIO2C7_SHIFT = 14,
- GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
- GPIO2C7_GPIO = 0,
- GPIO2C7_UART1_SOUT,
- GPIO2C7_TESTCLK_OUT1,
-
- GPIO2C6_SHIFT = 12,
- GPIO2C6_MASK = 1 << GPIO2C6_SHIFT,
- GPIO2C6_GPIO = 0,
- GPIO2C6_UART1_SIN,
-
- GPIO2C5_SHIFT = 10,
- GPIO2C5_MASK = 1 << GPIO2C5_SHIFT,
- GPIO2C5_GPIO = 0,
- GPIO2C5_I2C2_SCL,
-
- GPIO2C4_SHIFT = 8,
- GPIO2C4_MASK = 1 << GPIO2C4_SHIFT,
- GPIO2C4_GPIO = 0,
- GPIO2C4_I2C2_SDA,
-
- GPIO2C3_SHIFT = 6,
- GPIO2C3_MASK = 1 << GPIO2C3_SHIFT,
- GPIO2C3_GPIO = 0,
- GPIO2C3_MAC_TXD0,
-
- GPIO2C2_SHIFT = 4,
- GPIO2C2_MASK = 1 << GPIO2C2_SHIFT,
- GPIO2C2_GPIO = 0,
- GPIO2C2_MAC_TXD1,
-
- GPIO2C1_SHIFT = 2,
- GPIO2C1_MASK = 1 << GPIO2C1_SHIFT,
- GPIO2C1_GPIO = 0,
- GPIO2C1_MAC_RXD0,
-
- GPIO2C0_SHIFT = 0,
- GPIO2C0_MASK = 1 << GPIO2C0_SHIFT,
- GPIO2C0_GPIO = 0,
- GPIO2C0_MAC_RXD1,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
- GPIO2D6_SHIFT = 12,
- GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
- GPIO2D6_GPIO = 0,
- GPIO2D6_I2S_SDO1,
-
- GPIO2D5_SHIFT = 10,
- GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
- GPIO2D5_GPIO = 0,
- GPIO2D5_I2S_SDO2,
-
- GPIO2D4_SHIFT = 8,
- GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
- GPIO2D4_GPIO = 0,
- GPIO2D4_I2S_SDO3,
-
- GPIO2D1_SHIFT = 2,
- GPIO2D1_MASK = 1 << GPIO2D1_SHIFT,
- GPIO2D1_GPIO = 0,
- GPIO2D1_MAC_MDC,
-};
-
-struct rk3036_pinctrl_priv {
- struct rk3036_grf *grf;
-};
-
-static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id)
-{
- switch (pwm_id) {
- case PERIPH_ID_PWM0:
- rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
- GPIO0D2_PWM0 << GPIO0D2_SHIFT);
- break;
- case PERIPH_ID_PWM1:
- rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK,
- GPIO0A0_PWM1 << GPIO0A0_SHIFT);
- break;
- case PERIPH_ID_PWM2:
- rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK,
- GPIO0A1_PWM2 << GPIO0A1_SHIFT);
- break;
- case PERIPH_ID_PWM3:
- rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK,
- GPIO0D3_PWM3 << GPIO0D3_SHIFT);
- break;
- default:
- debug("pwm id = %d iomux error!\n", pwm_id);
- break;
- }
-}
-
-static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id)
-{
- switch (i2c_id) {
- case PERIPH_ID_I2C0:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A1_MASK | GPIO0A0_MASK,
- GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
- GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
-
- break;
- case PERIPH_ID_I2C1:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A3_MASK | GPIO0A2_MASK,
- GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
- GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
- break;
- case PERIPH_ID_I2C2:
- rk_clrsetreg(&grf->gpio2c_iomux,
- GPIO2C5_MASK | GPIO2C4_MASK,
- GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
- GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
-
- break;
- }
-}
-
-static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs)
-{
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D6_MASK,
- GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D7_MASK,
- GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT);
- break;
- }
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D5_MASK | GPIO1D4_MASK,
- GPIO1D5_SPI_TXD << GPIO1D5_SHIFT |
- GPIO1D4_SPI_RXD << GPIO1D4_SHIFT);
-
- rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A0_MASK,
- GPIO2A0_SPI_CLK << GPIO2A0_SHIFT);
-}
-
-static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id)
-{
- switch (uart_id) {
- case PERIPH_ID_UART0:
- rk_clrsetreg(&grf->gpio0c_iomux,
- GPIO0C3_MASK | GPIO0C2_MASK |
- GPIO0C1_MASK | GPIO0C0_MASK,
- GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT |
- GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT |
- GPIO0C1_UART0_SIN << GPIO0C1_SHIFT |
- GPIO0C0_UART0_SOUT << GPIO0C0_SHIFT);
- break;
- case PERIPH_ID_UART1:
- rk_clrsetreg(&grf->gpio2c_iomux,
- GPIO2C7_MASK | GPIO2C6_MASK,
- GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT |
- GPIO2C6_UART1_SIN << GPIO2C6_SHIFT);
- break;
- case PERIPH_ID_UART2:
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C3_MASK | GPIO1C2_MASK,
- GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
- GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
- break;
- }
-}
-
-static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id)
-{
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
- GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
- GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
- GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
- GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
- GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
- GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
- GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
- GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A4_MASK | GPIO2A1_MASK,
- GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT |
- GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT);
- break;
- case PERIPH_ID_SDCARD:
- rk_clrsetreg(&grf->gpio1c_iomux, 0xffff,
- GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT |
- GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT |
- GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT |
- GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT |
- GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT |
- GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT);
- break;
- }
-}
-
-static int rk3036_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%x, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- pinctrl_rk3036_pwm_config(priv->grf, func);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- pinctrl_rk3036_i2c_config(priv->grf, func);
- break;
- case PERIPH_ID_SPI0:
- pinctrl_rk3036_spi_config(priv->grf, flags);
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- pinctrl_rk3036_uart_config(priv->grf, func);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- pinctrl_rk3036_sdmmc_config(priv->grf, func);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk3036_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
- u32 cell[3];
- int ret;
-
- ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 14:
- return PERIPH_ID_SDCARD;
- case 16:
- return PERIPH_ID_EMMC;
- case 20:
- return PERIPH_ID_UART0;
- case 21:
- return PERIPH_ID_UART1;
- case 22:
- return PERIPH_ID_UART2;
- case 23:
- return PERIPH_ID_SPI0;
- case 24:
- return PERIPH_ID_I2C0;
- case 25:
- return PERIPH_ID_I2C1;
- case 26:
- return PERIPH_ID_I2C2;
- case 30:
- return PERIPH_ID_PWM0;
- }
- return -ENOENT;
-}
-
-static int rk3036_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk3036_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
- return rk3036_pinctrl_request(dev, func, 0);
-}
-
-static struct pinctrl_ops rk3036_pinctrl_ops = {
- .set_state_simple = rk3036_pinctrl_set_state_simple,
- .request = rk3036_pinctrl_request,
- .get_periph_id = rk3036_pinctrl_get_periph_id,
-};
-
-static int rk3036_pinctrl_probe(struct udevice *dev)
-{
- struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- debug("%s: grf=%p\n", __func__, priv->grf);
- return 0;
-}
-
-static const struct udevice_id rk3036_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3036-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3036) = {
- .name = "pinctrl_rk3036",
- .id = UCLASS_PINCTRL,
- .of_match = rk3036_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv),
- .ops = &rk3036_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
- .probe = rk3036_pinctrl_probe,
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Pinctrl driver for Rockchip 3128 SoCs
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3128.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct rk3128_pinctrl_priv {
- struct rk3128_grf *grf;
-};
-
-static void pinctrl_rk3128_i2c_config(struct rk3128_grf *grf, int i2c_id)
-{
- switch (i2c_id) {
- case PERIPH_ID_I2C0:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A1_MASK | GPIO0A0_MASK,
- GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
- GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
-
- break;
- case PERIPH_ID_I2C1:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A3_MASK | GPIO0A2_MASK,
- GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
- GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
- break;
- case PERIPH_ID_I2C2:
- rk_clrsetreg(&grf->gpio2c_iomux2,
- GPIO2C5_MASK | GPIO2C4_MASK,
- GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
- GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
- break;
- case PERIPH_ID_I2C3:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A7_MASK | GPIO0A6_MASK,
- GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
- GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
-
- break;
- }
-}
-
-static void pinctrl_rk3128_sdmmc_config(struct rk3128_grf *grf, int mmc_id)
-{
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
- GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
- GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
- GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
- GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
- GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
- GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
- GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
- GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A5_MASK | GPIO2A7_MASK,
- GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
- GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
- break;
- case PERIPH_ID_SDCARD:
- rk_clrsetreg(&grf->gpio1c_iomux, 0x0fff,
- GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT |
- GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT |
- GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT |
- GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT |
- GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT |
- GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT);
- break;
- }
-}
-
-static int rk3128_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk3128_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%x, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- pinctrl_rk3128_i2c_config(priv->grf, func);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- pinctrl_rk3128_sdmmc_config(priv->grf, func);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk3128_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
- u32 cell[3];
- int ret;
-
- ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
- "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 14:
- return PERIPH_ID_SDCARD;
- case 16:
- return PERIPH_ID_EMMC;
- case 20:
- return PERIPH_ID_UART0;
- case 21:
- return PERIPH_ID_UART1;
- case 22:
- return PERIPH_ID_UART2;
- case 23:
- return PERIPH_ID_SPI0;
- case 24:
- return PERIPH_ID_I2C0;
- case 25:
- return PERIPH_ID_I2C1;
- case 26:
- return PERIPH_ID_I2C2;
- case 27:
- return PERIPH_ID_I2C3;
- case 30:
- return PERIPH_ID_PWM0;
- }
- return -ENOENT;
-}
-
-static int rk3128_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk3128_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
- return rk3128_pinctrl_request(dev, func, 0);
-}
-
-static struct pinctrl_ops rk3128_pinctrl_ops = {
- .set_state_simple = rk3128_pinctrl_set_state_simple,
- .request = rk3128_pinctrl_request,
- .get_periph_id = rk3128_pinctrl_get_periph_id,
-};
-
-static int rk3128_pinctrl_probe(struct udevice *dev)
-{
- struct rk3128_pinctrl_priv *priv = dev_get_priv(dev);
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- debug("%s: grf=%p\n", __func__, priv->grf);
- return 0;
-}
-
-static const struct udevice_id rk3128_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3128-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3128) = {
- .name = "pinctrl_rk3128",
- .id = UCLASS_PINCTRL,
- .of_match = rk3128_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk3128_pinctrl_priv),
- .ops = &rk3128_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
- .probe = rk3128_pinctrl_probe,
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Pinctrl driver for Rockchip RK3188 SoCs
- * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3188.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3188.h>
-#include <dm/pinctrl.h>
-#include <dm/root.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* GRF_GPIO0D_IOMUX */
-enum {
- GPIO0D7_SHIFT = 14,
- GPIO0D7_MASK = 1,
- GPIO0D7_GPIO = 0,
- GPIO0D7_SPI1_CSN0,
-
- GPIO0D6_SHIFT = 12,
- GPIO0D6_MASK = 1,
- GPIO0D6_GPIO = 0,
- GPIO0D6_SPI1_CLK,
-
- GPIO0D5_SHIFT = 10,
- GPIO0D5_MASK = 1,
- GPIO0D5_GPIO = 0,
- GPIO0D5_SPI1_TXD,
-
- GPIO0D4_SHIFT = 8,
- GPIO0D4_MASK = 1,
- GPIO0D4_GPIO = 0,
- GPIO0D4_SPI0_RXD,
-
- GPIO0D3_SHIFT = 6,
- GPIO0D3_MASK = 3,
- GPIO0D3_GPIO = 0,
- GPIO0D3_FLASH_CSN3,
- GPIO0D3_EMMC_RSTN_OUT,
-
- GPIO0D2_SHIFT = 4,
- GPIO0D2_MASK = 3,
- GPIO0D2_GPIO = 0,
- GPIO0D2_FLASH_CSN2,
- GPIO0D2_EMMC_CMD,
-
- GPIO0D1_SHIFT = 2,
- GPIO0D1_MASK = 1,
- GPIO0D1_GPIO = 0,
- GPIO0D1_FLASH_CSN1,
-
- GPIO0D0_SHIFT = 0,
- GPIO0D0_MASK = 3,
- GPIO0D0_GPIO = 0,
- GPIO0D0_FLASH_DQS,
- GPIO0D0_EMMC_CLKOUT
-};
-
-/* GRF_GPIO1A_IOMUX */
-enum {
- GPIO1A7_SHIFT = 14,
- GPIO1A7_MASK = 3,
- GPIO1A7_GPIO = 0,
- GPIO1A7_UART1_RTS_N,
- GPIO1A7_SPI0_CSN0,
-
- GPIO1A6_SHIFT = 12,
- GPIO1A6_MASK = 3,
- GPIO1A6_GPIO = 0,
- GPIO1A6_UART1_CTS_N,
- GPIO1A6_SPI0_CLK,
-
- GPIO1A5_SHIFT = 10,
- GPIO1A5_MASK = 3,
- GPIO1A5_GPIO = 0,
- GPIO1A5_UART1_SOUT,
- GPIO1A5_SPI0_TXD,
-
- GPIO1A4_SHIFT = 8,
- GPIO1A4_MASK = 3,
- GPIO1A4_GPIO = 0,
- GPIO1A4_UART1_SIN,
- GPIO1A4_SPI0_RXD,
-
- GPIO1A3_SHIFT = 6,
- GPIO1A3_MASK = 1,
- GPIO1A3_GPIO = 0,
- GPIO1A3_UART0_RTS_N,
-
- GPIO1A2_SHIFT = 4,
- GPIO1A2_MASK = 1,
- GPIO1A2_GPIO = 0,
- GPIO1A2_UART0_CTS_N,
-
- GPIO1A1_SHIFT = 2,
- GPIO1A1_MASK = 1,
- GPIO1A1_GPIO = 0,
- GPIO1A1_UART0_SOUT,
-
- GPIO1A0_SHIFT = 0,
- GPIO1A0_MASK = 1,
- GPIO1A0_GPIO = 0,
- GPIO1A0_UART0_SIN,
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK = 1,
- GPIO1B7_GPIO = 0,
- GPIO1B7_SPI0_CSN1,
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK = 3,
- GPIO1B6_GPIO = 0,
- GPIO1B6_SPDIF_TX,
- GPIO1B6_SPI1_CSN1,
-
- GPIO1B5_SHIFT = 10,
- GPIO1B5_MASK = 3,
- GPIO1B5_GPIO = 0,
- GPIO1B5_UART3_RTS_N,
- GPIO1B5_RESERVED,
-
- GPIO1B4_SHIFT = 8,
- GPIO1B4_MASK = 3,
- GPIO1B4_GPIO = 0,
- GPIO1B4_UART3_CTS_N,
- GPIO1B4_GPS_RFCLK,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK = 3,
- GPIO1B3_GPIO = 0,
- GPIO1B3_UART3_SOUT,
- GPIO1B3_GPS_SIG,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK = 3,
- GPIO1B2_GPIO = 0,
- GPIO1B2_UART3_SIN,
- GPIO1B2_GPS_MAG,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 3,
- GPIO1B1_GPIO = 0,
- GPIO1B1_UART2_SOUT,
- GPIO1B1_JTAG_TDO,
-
- GPIO1B0_SHIFT = 0,
- GPIO1B0_MASK = 3,
- GPIO1B0_GPIO = 0,
- GPIO1B0_UART2_SIN,
- GPIO1B0_JTAG_TDI,
-};
-
-/* GRF_GPIO1D_IOMUX */
-enum {
- GPIO1D7_SHIFT = 14,
- GPIO1D7_MASK = 1,
- GPIO1D7_GPIO = 0,
- GPIO1D7_I2C4_SCL,
-
- GPIO1D6_SHIFT = 12,
- GPIO1D6_MASK = 1,
- GPIO1D6_GPIO = 0,
- GPIO1D6_I2C4_SDA,
-
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK = 1,
- GPIO1D5_GPIO = 0,
- GPIO1D5_I2C2_SCL,
-
- GPIO1D4_SHIFT = 8,
- GPIO1D4_MASK = 1,
- GPIO1D4_GPIO = 0,
- GPIO1D4_I2C2_SDA,
-
- GPIO1D3_SHIFT = 6,
- GPIO1D3_MASK = 1,
- GPIO1D3_GPIO = 0,
- GPIO1D3_I2C1_SCL,
-
- GPIO1D2_SHIFT = 4,
- GPIO1D2_MASK = 1,
- GPIO1D2_GPIO = 0,
- GPIO1D2_I2C1_SDA,
-
- GPIO1D1_SHIFT = 2,
- GPIO1D1_MASK = 1,
- GPIO1D1_GPIO = 0,
- GPIO1D1_I2C0_SCL,
-
- GPIO1D0_SHIFT = 0,
- GPIO1D0_MASK = 1,
- GPIO1D0_GPIO = 0,
- GPIO1D0_I2C0_SDA,
-};
-
-/* GRF_GPIO3A_IOMUX */
-enum {
- GPIO3A7_SHIFT = 14,
- GPIO3A7_MASK = 1,
- GPIO3A7_GPIO = 0,
- GPIO3A7_SDMMC0_DATA3,
-
- GPIO3A6_SHIFT = 12,
- GPIO3A6_MASK = 1,
- GPIO3A6_GPIO = 0,
- GPIO3A6_SDMMC0_DATA2,
-
- GPIO3A5_SHIFT = 10,
- GPIO3A5_MASK = 1,
- GPIO3A5_GPIO = 0,
- GPIO3A5_SDMMC0_DATA1,
-
- GPIO3A4_SHIFT = 8,
- GPIO3A4_MASK = 1,
- GPIO3A4_GPIO = 0,
- GPIO3A4_SDMMC0_DATA0,
-
- GPIO3A3_SHIFT = 6,
- GPIO3A3_MASK = 1,
- GPIO3A3_GPIO = 0,
- GPIO3A3_SDMMC0_CMD,
-
- GPIO3A2_SHIFT = 4,
- GPIO3A2_MASK = 1,
- GPIO3A2_GPIO = 0,
- GPIO3A2_SDMMC0_CLKOUT,
-
- GPIO3A1_SHIFT = 2,
- GPIO3A1_MASK = 1,
- GPIO3A1_GPIO = 0,
- GPIO3A1_SDMMC0_PWREN,
-
- GPIO3A0_SHIFT = 0,
- GPIO3A0_MASK = 1,
- GPIO3A0_GPIO = 0,
- GPIO3A0_SDMMC0_RSTN,
-};
-
-/* GRF_GPIO3B_IOMUX */
-enum {
- GPIO3B7_SHIFT = 14,
- GPIO3B7_MASK = 3,
- GPIO3B7_GPIO = 0,
- GPIO3B7_CIF_DATA11,
- GPIO3B7_I2C3_SCL,
-
- GPIO3B6_SHIFT = 12,
- GPIO3B6_MASK = 3,
- GPIO3B6_GPIO = 0,
- GPIO3B6_CIF_DATA10,
- GPIO3B6_I2C3_SDA,
-
- GPIO3B5_SHIFT = 10,
- GPIO3B5_MASK = 3,
- GPIO3B5_GPIO = 0,
- GPIO3B5_CIF_DATA1,
- GPIO3B5_HSADC_DATA9,
-
- GPIO3B4_SHIFT = 8,
- GPIO3B4_MASK = 3,
- GPIO3B4_GPIO = 0,
- GPIO3B4_CIF_DATA0,
- GPIO3B4_HSADC_DATA8,
-
- GPIO3B3_SHIFT = 6,
- GPIO3B3_MASK = 1,
- GPIO3B3_GPIO = 0,
- GPIO3B3_CIF_CLKOUT,
-
- GPIO3B2_SHIFT = 4,
- GPIO3B2_MASK = 1,
- GPIO3B2_GPIO = 0,
- /* no muxes */
-
- GPIO3B1_SHIFT = 2,
- GPIO3B1_MASK = 1,
- GPIO3B1_GPIO = 0,
- GPIO3B1_SDMMC0_WRITE_PRT,
-
- GPIO3B0_SHIFT = 0,
- GPIO3B0_MASK = 1,
- GPIO3B0_GPIO = 0,
- GPIO3B0_SDMMC_DETECT_N,
-};
-
-/* GRF_GPIO3C_IOMUX */
-enum {
- GPIO3C7_SHIFT = 14,
- GPIO3C7_MASK = 3,
- GPIO3C7_GPIO = 0,
- GPIO3C7_SDMMC1_WRITE_PRT,
- GPIO3C7_RMII_CRS_DVALID,
- GPIO3C7_RESERVED,
-
- GPIO3C6_SHIFT = 12,
- GPIO3C6_MASK = 3,
- GPIO3C6_GPIO = 0,
- GPIO3C6_SDMMC1_DECTN,
- GPIO3C6_RMII_RX_ERR,
- GPIO3C6_RESERVED,
-
- GPIO3C5_SHIFT = 10,
- GPIO3C5_MASK = 3,
- GPIO3C5_GPIO = 0,
- GPIO3C5_SDMMC1_CLKOUT,
- GPIO3C5_RMII_CLKOUT,
- GPIO3C5_RMII_CLKIN,
-
- GPIO3C4_SHIFT = 8,
- GPIO3C4_MASK = 3,
- GPIO3C4_GPIO = 0,
- GPIO3C4_SDMMC1_DATA3,
- GPIO3C4_RMII_RXD1,
- GPIO3C4_RESERVED,
-
- GPIO3C3_SHIFT = 6,
- GPIO3C3_MASK = 3,
- GPIO3C3_GPIO = 0,
- GPIO3C3_SDMMC1_DATA2,
- GPIO3C3_RMII_RXD0,
- GPIO3C3_RESERVED,
-
- GPIO3C2_SHIFT = 4,
- GPIO3C2_MASK = 3,
- GPIO3C2_GPIO = 0,
- GPIO3C2_SDMMC1_DATA1,
- GPIO3C2_RMII_TXD0,
- GPIO3C2_RESERVED,
-
- GPIO3C1_SHIFT = 2,
- GPIO3C1_MASK = 3,
- GPIO3C1_GPIO = 0,
- GPIO3C1_SDMMC1_DATA0,
- GPIO3C1_RMII_TXD1,
- GPIO3C1_RESERVED,
-
- GPIO3C0_SHIFT = 0,
- GPIO3C0_MASK = 3,
- GPIO3C0_GPIO = 0,
- GPIO3C0_SDMMC1_CMD,
- GPIO3C0_RMII_TX_EN,
- GPIO3C0_RESERVED,
-};
-
-/* GRF_GPIO3D_IOMUX */
-enum {
- GPIO3D6_SHIFT = 12,
- GPIO3D6_MASK = 3,
- GPIO3D6_GPIO = 0,
- GPIO3D6_PWM_3,
- GPIO3D6_JTAG_TMS,
- GPIO3D6_HOST_DRV_VBUS,
-
- GPIO3D5_SHIFT = 10,
- GPIO3D5_MASK = 3,
- GPIO3D5_GPIO = 0,
- GPIO3D5_PWM_2,
- GPIO3D5_JTAG_TCK,
- GPIO3D5_OTG_DRV_VBUS,
-
- GPIO3D4_SHIFT = 8,
- GPIO3D4_MASK = 3,
- GPIO3D4_GPIO = 0,
- GPIO3D4_PWM_1,
- GPIO3D4_JTAG_TRSTN,
-
- GPIO3D3_SHIFT = 6,
- GPIO3D3_MASK = 3,
- GPIO3D3_GPIO = 0,
- GPIO3D3_PWM_0,
-
- GPIO3D2_SHIFT = 4,
- GPIO3D2_MASK = 3,
- GPIO3D2_GPIO = 0,
- GPIO3D2_SDMMC1_INT_N,
-
- GPIO3D1_SHIFT = 2,
- GPIO3D1_MASK = 3,
- GPIO3D1_GPIO = 0,
- GPIO3D1_SDMMC1_BACKEND_PWR,
- GPIO3D1_MII_MDCLK,
-
- GPIO3D0_SHIFT = 0,
- GPIO3D0_MASK = 3,
- GPIO3D0_GPIO = 0,
- GPIO3D0_SDMMC1_PWR_EN,
- GPIO3D0_MII_MD,
-};
-
-struct rk3188_pinctrl_priv {
- struct rk3188_grf *grf;
- struct rk3188_pmu *pmu;
- int num_banks;
-};
-
-/**
- * Encode variants of iomux registers into a type variable
- */
-#define IOMUX_GPIO_ONLY BIT(0)
-
-/**
- * @type: iomux variant using IOMUX_* constants
- * @offset: if initialized to -1 it will be autocalculated, by specifying
- * an initial offset value the relevant source offset can be reset
- * to a new value for autocalculating the following iomux registers.
- */
-struct rockchip_iomux {
- u8 type;
- s16 offset;
-};
-
-/**
- * @reg: register offset of the gpio bank
- * @nr_pins: number of pins in this bank
- * @bank_num: number of the bank, to account for holes
- * @name: name of the bank
- * @iomux: array describing the 4 iomux sources of the bank
- */
-struct rockchip_pin_bank {
- u16 reg;
- u8 nr_pins;
- u8 bank_num;
- char *name;
- struct rockchip_iomux iomux[4];
-};
-
-#define PIN_BANK(id, pins, label) \
- { \
- .bank_num = id, \
- .nr_pins = pins, \
- .name = label, \
- .iomux = { \
- { .offset = -1 }, \
- { .offset = -1 }, \
- { .offset = -1 }, \
- { .offset = -1 }, \
- }, \
- }
-
-#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
- { \
- .bank_num = id, \
- .nr_pins = pins, \
- .name = label, \
- .iomux = { \
- { .type = iom0, .offset = -1 }, \
- { .type = iom1, .offset = -1 }, \
- { .type = iom2, .offset = -1 }, \
- { .type = iom3, .offset = -1 }, \
- }, \
- }
-
-#ifndef CONFIG_SPL_BUILD
-static struct rockchip_pin_bank rk3188_pin_banks[] = {
- PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
- PIN_BANK(1, 32, "gpio1"),
- PIN_BANK(2, 32, "gpio2"),
- PIN_BANK(3, 32, "gpio3"),
-};
-#endif
-
-static void pinctrl_rk3188_pwm_config(struct rk3188_grf *grf, int pwm_id)
-{
- switch (pwm_id) {
- case PERIPH_ID_PWM0:
- rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D3_MASK << GPIO3D3_SHIFT,
- GPIO3D3_PWM_0 << GPIO3D3_SHIFT);
- break;
- case PERIPH_ID_PWM1:
- rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D4_MASK << GPIO3D4_SHIFT,
- GPIO3D4_PWM_1 << GPIO3D4_SHIFT);
- break;
- case PERIPH_ID_PWM2:
- rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D5_MASK << GPIO3D5_SHIFT,
- GPIO3D5_PWM_2 << GPIO3D5_SHIFT);
- break;
- case PERIPH_ID_PWM3:
- rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D6_MASK << GPIO3D6_SHIFT,
- GPIO3D6_PWM_3 << GPIO3D6_SHIFT);
- break;
- default:
- debug("pwm id = %d iomux error!\n", pwm_id);
- break;
- }
-}
-
-static void pinctrl_rk3188_i2c_config(struct rk3188_grf *grf,
- struct rk3188_pmu *pmu, int i2c_id)
-{
- switch (i2c_id) {
- case PERIPH_ID_I2C0:
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D1_MASK << GPIO1D1_SHIFT |
- GPIO1D0_MASK << GPIO1D0_SHIFT,
- GPIO1D1_I2C0_SCL << GPIO1D1_SHIFT |
- GPIO1D0_I2C0_SDA << GPIO1D0_SHIFT);
- /* enable new i2c controller */
- rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT,
- 1 << RKI2C0_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C1:
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D3_MASK << GPIO1D3_SHIFT |
- GPIO1D2_MASK << GPIO1D2_SHIFT,
- GPIO1D3_I2C1_SCL << GPIO1D2_SHIFT |
- GPIO1D2_I2C1_SDA << GPIO1D2_SHIFT);
- rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT,
- 1 << RKI2C1_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C2:
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D5_MASK << GPIO1D5_SHIFT |
- GPIO1D4_MASK << GPIO1D4_SHIFT,
- GPIO1D5_I2C2_SCL << GPIO1D5_SHIFT |
- GPIO1D4_I2C2_SDA << GPIO1D4_SHIFT);
- rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT,
- 1 << RKI2C2_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C3:
- rk_clrsetreg(&grf->gpio3b_iomux,
- GPIO3B7_MASK << GPIO3B7_SHIFT |
- GPIO3B6_MASK << GPIO3B6_SHIFT,
- GPIO3B7_I2C3_SCL << GPIO3B7_SHIFT |
- GPIO3B6_I2C3_SDA << GPIO3B6_SHIFT);
- rk_clrsetreg(&grf->soc_con1, 1 << RKI2C3_SEL_SHIFT,
- 1 << RKI2C3_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C4:
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D7_MASK << GPIO1D7_SHIFT |
- GPIO1D6_MASK << GPIO1D6_SHIFT,
- GPIO1D7_I2C4_SCL << GPIO1D7_SHIFT |
- GPIO1D6_I2C4_SDA << GPIO1D6_SHIFT);
- rk_clrsetreg(&grf->soc_con1, 1 << RKI2C4_SEL_SHIFT,
- 1 << RKI2C4_SEL_SHIFT);
- break;
- default:
- debug("i2c id = %d iomux error!\n", i2c_id);
- break;
- }
-}
-
-static int pinctrl_rk3188_spi_config(struct rk3188_grf *grf,
- enum periph_id spi_id, int cs)
-{
- switch (spi_id) {
- case PERIPH_ID_SPI0:
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio1a_iomux,
- GPIO1A7_MASK << GPIO1A7_SHIFT,
- GPIO1A7_SPI0_CSN0 << GPIO1A7_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B7_MASK << GPIO1B7_SHIFT,
- GPIO1B7_SPI0_CSN1 << GPIO1B7_SHIFT);
- break;
- default:
- goto err;
- }
- rk_clrsetreg(&grf->gpio1a_iomux,
- GPIO1A4_MASK << GPIO1A4_SHIFT |
- GPIO1A5_MASK << GPIO1A5_SHIFT |
- GPIO1A6_MASK << GPIO1A6_SHIFT,
- GPIO1A4_SPI0_RXD << GPIO1A4_SHIFT |
- GPIO1A5_SPI0_TXD << GPIO1A5_SHIFT |
- GPIO1A6_SPI0_CLK << GPIO1A6_SHIFT);
- break;
- case PERIPH_ID_SPI1:
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio0d_iomux,
- GPIO0D7_MASK << GPIO0D7_SHIFT,
- GPIO0D7_SPI1_CSN0 << GPIO0D7_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B6_MASK << GPIO1B6_SHIFT,
- GPIO1B6_SPI1_CSN1 << GPIO1B6_SHIFT);
- break;
- default:
- goto err;
- }
- rk_clrsetreg(&grf->gpio0d_iomux,
- GPIO0D4_MASK << GPIO0D4_SHIFT |
- GPIO0D5_MASK << GPIO0D5_SHIFT |
- GPIO0D6_MASK << GPIO0D6_SHIFT,
- GPIO0D4_SPI0_RXD << GPIO0D4_SHIFT |
- GPIO0D5_SPI1_TXD << GPIO0D5_SHIFT |
- GPIO0D6_SPI1_CLK << GPIO0D6_SHIFT);
- break;
- default:
- goto err;
- }
-
- return 0;
-err:
- debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
- return -ENOENT;
-}
-
-static void pinctrl_rk3188_uart_config(struct rk3188_grf *grf, int uart_id)
-{
- switch (uart_id) {
- case PERIPH_ID_UART0:
- rk_clrsetreg(&grf->gpio1a_iomux,
- GPIO1A3_MASK << GPIO1A3_SHIFT |
- GPIO1A2_MASK << GPIO1A2_SHIFT |
- GPIO1A1_MASK << GPIO1A1_SHIFT |
- GPIO1A0_MASK << GPIO1A0_SHIFT,
- GPIO1A3_UART0_RTS_N << GPIO1A3_SHIFT |
- GPIO1A2_UART0_CTS_N << GPIO1A2_SHIFT |
- GPIO1A1_UART0_SOUT << GPIO1A1_SHIFT |
- GPIO1A0_UART0_SIN << GPIO1A0_SHIFT);
- break;
- case PERIPH_ID_UART1:
- rk_clrsetreg(&grf->gpio1a_iomux,
- GPIO1A7_MASK << GPIO1A7_SHIFT |
- GPIO1A6_MASK << GPIO1A6_SHIFT |
- GPIO1A5_MASK << GPIO1A5_SHIFT |
- GPIO1A4_MASK << GPIO1A4_SHIFT,
- GPIO1A7_UART1_RTS_N << GPIO1A7_SHIFT |
- GPIO1A6_UART1_CTS_N << GPIO1A6_SHIFT |
- GPIO1A5_UART1_SOUT << GPIO1A5_SHIFT |
- GPIO1A4_UART1_SIN << GPIO1A4_SHIFT);
- break;
- case PERIPH_ID_UART2:
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B1_MASK << GPIO1B1_SHIFT |
- GPIO1B0_MASK << GPIO1B0_SHIFT,
- GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
- GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
- break;
- case PERIPH_ID_UART3:
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B5_MASK << GPIO1B5_SHIFT |
- GPIO1B4_MASK << GPIO1B4_SHIFT |
- GPIO1B3_MASK << GPIO1B3_SHIFT |
- GPIO1B2_MASK << GPIO1B2_SHIFT,
- GPIO1B5_UART3_RTS_N << GPIO1B5_SHIFT |
- GPIO1B4_UART3_CTS_N << GPIO1B4_SHIFT |
- GPIO1B3_UART3_SOUT << GPIO1B3_SHIFT |
- GPIO1B2_UART3_SIN << GPIO1B2_SHIFT);
- break;
- default:
- debug("uart id = %d iomux error!\n", uart_id);
- break;
- }
-}
-
-static void pinctrl_rk3188_sdmmc_config(struct rk3188_grf *grf, int mmc_id)
-{
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- rk_clrsetreg(&grf->soc_con0, 1 << EMMC_FLASH_SEL_SHIFT,
- 1 << EMMC_FLASH_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio0d_iomux,
- GPIO0D2_MASK << GPIO0D2_SHIFT |
- GPIO0D0_MASK << GPIO0D0_SHIFT,
- GPIO0D2_EMMC_CMD << GPIO0D2_SHIFT |
- GPIO0D0_EMMC_CLKOUT << GPIO0D0_SHIFT);
- break;
- case PERIPH_ID_SDCARD:
- rk_clrsetreg(&grf->gpio3b_iomux,
- GPIO3B0_MASK << GPIO3B0_SHIFT,
- GPIO3B0_SDMMC_DETECT_N << GPIO3B0_SHIFT);
- rk_clrsetreg(&grf->gpio3a_iomux,
- GPIO3A7_MASK << GPIO3A7_SHIFT |
- GPIO3A6_MASK << GPIO3A6_SHIFT |
- GPIO3A5_MASK << GPIO3A5_SHIFT |
- GPIO3A4_MASK << GPIO3A4_SHIFT |
- GPIO3A3_MASK << GPIO3A3_SHIFT |
- GPIO3A3_MASK << GPIO3A2_SHIFT,
- GPIO3A7_SDMMC0_DATA3 << GPIO3A7_SHIFT |
- GPIO3A6_SDMMC0_DATA2 << GPIO3A6_SHIFT |
- GPIO3A5_SDMMC0_DATA1 << GPIO3A5_SHIFT |
- GPIO3A4_SDMMC0_DATA0 << GPIO3A4_SHIFT |
- GPIO3A3_SDMMC0_CMD << GPIO3A3_SHIFT |
- GPIO3A2_SDMMC0_CLKOUT << GPIO3A2_SHIFT);
- break;
- default:
- debug("mmc id = %d iomux error!\n", mmc_id);
- break;
- }
-}
-
-static int rk3188_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%x, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- case PERIPH_ID_PWM4:
- pinctrl_rk3188_pwm_config(priv->grf, func);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- pinctrl_rk3188_i2c_config(priv->grf, priv->pmu, func);
- break;
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- case PERIPH_ID_SPI2:
- pinctrl_rk3188_spi_config(priv->grf, func, flags);
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- case PERIPH_ID_UART4:
- pinctrl_rk3188_uart_config(priv->grf, func);
- break;
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- pinctrl_rk3188_sdmmc_config(priv->grf, func);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk3188_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- u32 cell[3];
- int ret;
-
- ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 44:
- return PERIPH_ID_SPI0;
- case 45:
- return PERIPH_ID_SPI1;
- case 46:
- return PERIPH_ID_SPI2;
- case 60:
- return PERIPH_ID_I2C0;
- case 62: /* Note strange order */
- return PERIPH_ID_I2C1;
- case 61:
- return PERIPH_ID_I2C2;
- case 63:
- return PERIPH_ID_I2C3;
- case 64:
- return PERIPH_ID_I2C4;
- case 65:
- return PERIPH_ID_I2C5;
- }
-#endif
-
- return -ENOENT;
-}
-
-static int rk3188_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk3188_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
- return rk3188_pinctrl_request(dev, func, 0);
-}
-
-#ifndef CONFIG_SPL_BUILD
-int rk3188_pinctrl_get_pin_info(struct rk3188_pinctrl_priv *priv,
- int banknum, int ind, u32 **addrp, uint *shiftp,
- uint *maskp)
-{
- struct rockchip_pin_bank *bank = &rk3188_pin_banks[banknum];
- uint muxnum;
- u32 *addr;
-
- for (muxnum = 0; muxnum < 4; muxnum++) {
- struct rockchip_iomux *mux = &bank->iomux[muxnum];
-
- if (ind >= 8) {
- ind -= 8;
- continue;
- }
-
- addr = &priv->grf->gpio0c_iomux - 2;
- addr += mux->offset;
- *shiftp = ind & 7;
- *maskp = 3;
- *shiftp *= 2;
-
- debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
- *maskp, *shiftp);
- *addrp = addr;
- return 0;
- }
-
- return -EINVAL;
-}
-
-static int rk3188_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
- int index)
-{
- struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
- uint shift;
- uint mask;
- u32 *addr;
- int ret;
-
- ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
- &mask);
- if (ret)
- return ret;
- return (readl(addr) & mask) >> shift;
-}
-
-static int rk3188_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
- int muxval, int flags)
-{
- struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
- uint shift, ind = index;
- uint mask;
- u32 *addr;
- int ret;
-
- debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
- ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
- &mask);
- if (ret)
- return ret;
- rk_clrsetreg(addr, mask << shift, muxval << shift);
-
- /* Handle pullup/pulldown */
- if (flags) {
- uint val = 0;
-
- if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
- val = 1;
- else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
- val = 2;
-
- ind = index >> 3;
-
- if (banknum == 0 && index < 12) {
- addr = &priv->pmu->gpio0_p[ind];
- shift = (index & 7) * 2;
- } else if (banknum == 0 && index >= 12) {
- addr = &priv->grf->gpio0_p[ind - 1];
- /*
- * The bits in the grf-registers have an inverse
- * ordering with the lowest pin being in bits 15:14
- * and the highest pin in bits 1:0 .
- */
- shift = (7 - (index & 7)) * 2;
- } else {
- addr = &priv->grf->gpio1_p[banknum - 1][ind];
- shift = (7 - (index & 7)) * 2;
- }
- debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
- shift);
- rk_clrsetreg(addr, 3 << shift, val << shift);
- }
-
- return 0;
-}
-
-static int rk3188_pinctrl_set_state(struct udevice *dev, struct udevice *config)
-{
- const void *blob = gd->fdt_blob;
- int pcfg_node, ret, flags, count, i;
- u32 cell[60], *ptr;
-
- debug("%s: %s %s\n", __func__, dev->name, config->name);
- ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
- "rockchip,pins", cell,
- ARRAY_SIZE(cell));
- if (ret < 0) {
- debug("%s: bad array %d\n", __func__, ret);
- return -EINVAL;
- }
- count = ret;
- for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
- pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
- if (pcfg_node < 0)
- return -EINVAL;
- flags = pinctrl_decode_pin_config(blob, pcfg_node);
- if (flags < 0)
- return flags;
-
- ret = rk3188_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
- flags);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
-static struct pinctrl_ops rk3188_pinctrl_ops = {
-#ifndef CONFIG_SPL_BUILD
- .set_state = rk3188_pinctrl_set_state,
- .get_gpio_mux = rk3188_pinctrl_get_gpio_mux,
-#endif
- .set_state_simple = rk3188_pinctrl_set_state_simple,
- .request = rk3188_pinctrl_request,
- .get_periph_id = rk3188_pinctrl_get_periph_id,
-};
-
-#ifndef CONFIG_SPL_BUILD
-static int rk3188_pinctrl_parse_tables(struct rk3188_pinctrl_priv *priv,
- struct rockchip_pin_bank *banks,
- int count)
-{
- struct rockchip_pin_bank *bank;
- uint reg, muxnum, banknum;
-
- reg = 0;
- for (banknum = 0; banknum < count; banknum++) {
- bank = &banks[banknum];
- bank->reg = reg;
- debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
- for (muxnum = 0; muxnum < 4; muxnum++) {
- struct rockchip_iomux *mux = &bank->iomux[muxnum];
-
- mux->offset = reg;
- reg += 1;
- }
- }
-
- return 0;
-}
-#endif
-
-static int rk3188_pinctrl_probe(struct udevice *dev)
-{
- struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
- int ret = 0;
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
- debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
-#ifndef CONFIG_SPL_BUILD
- ret = rk3188_pinctrl_parse_tables(priv, rk3188_pin_banks,
- ARRAY_SIZE(rk3188_pin_banks));
-#endif
-
- return ret;
-}
-
-static const struct udevice_id rk3188_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3188-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3188) = {
- .name = "rockchip_rk3188_pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = rk3188_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk3188_pinctrl_priv),
- .ops = &rk3188_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- .bind = dm_scan_fdt_dev,
-#endif
- .probe = rk3188_pinctrl_probe,
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk322x.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* GRF_GPIO0A_IOMUX */
-enum {
- GPIO0A7_SHIFT = 14,
- GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
- GPIO0A7_GPIO = 0,
- GPIO0A7_I2C3_SDA,
- GPIO0A7_HDMI_DDCSDA,
-
- GPIO0A6_SHIFT = 12,
- GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
- GPIO0A6_GPIO = 0,
- GPIO0A6_I2C3_SCL,
- GPIO0A6_HDMI_DDCSCL,
-
- GPIO0A3_SHIFT = 6,
- GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
- GPIO0A3_GPIO = 0,
- GPIO0A3_I2C1_SDA,
- GPIO0A3_SDIO_CMD,
-
- GPIO0A2_SHIFT = 4,
- GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
- GPIO0A2_GPIO = 0,
- GPIO0A2_I2C1_SCL,
-
- GPIO0A1_SHIFT = 2,
- GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
- GPIO0A1_GPIO = 0,
- GPIO0A1_I2C0_SDA,
-
- GPIO0A0_SHIFT = 0,
- GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
- GPIO0A0_GPIO = 0,
- GPIO0A0_I2C0_SCL,
-};
-
-/* GRF_GPIO0B_IOMUX */
-enum {
- GPIO0B7_SHIFT = 14,
- GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
- GPIO0B7_GPIO = 0,
- GPIO0B7_HDMI_HDP,
-
- GPIO0B6_SHIFT = 12,
- GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
- GPIO0B6_GPIO = 0,
- GPIO0B6_I2S_SDI,
- GPIO0B6_SPI_CSN0,
-
- GPIO0B5_SHIFT = 10,
- GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
- GPIO0B5_GPIO = 0,
- GPIO0B5_I2S_SDO,
- GPIO0B5_SPI_RXD,
-
- GPIO0B3_SHIFT = 6,
- GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
- GPIO0B3_GPIO = 0,
- GPIO0B3_I2S1_LRCKRX,
- GPIO0B3_SPI_TXD,
-
- GPIO0B1_SHIFT = 2,
- GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
- GPIO0B1_GPIO = 0,
- GPIO0B1_I2S_SCLK,
- GPIO0B1_SPI_CLK,
-
- GPIO0B0_SHIFT = 0,
- GPIO0B0_MASK = 3,
- GPIO0B0_GPIO = 0,
- GPIO0B0_I2S_MCLK,
-};
-
-/* GRF_GPIO0C_IOMUX */
-enum {
- GPIO0C4_SHIFT = 8,
- GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
- GPIO0C4_GPIO = 0,
- GPIO0C4_HDMI_CECSDA,
-
- GPIO0C1_SHIFT = 2,
- GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
- GPIO0C1_GPIO = 0,
- GPIO0C1_UART0_RSTN,
- GPIO0C1_CLK_OUT1,
-};
-
-/* GRF_GPIO0D_IOMUX */
-enum {
- GPIO0D6_SHIFT = 12,
- GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
- GPIO0D6_GPIO = 0,
- GPIO0D6_SDIO_PWREN,
- GPIO0D6_PWM11,
-
- GPIO0D4_SHIFT = 8,
- GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
- GPIO0D4_GPIO = 0,
- GPIO0D4_PWM2,
-
- GPIO0D3_SHIFT = 6,
- GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
- GPIO0D3_GPIO = 0,
- GPIO0D3_PWM1,
-
- GPIO0D2_SHIFT = 4,
- GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
- GPIO0D2_GPIO = 0,
- GPIO0D2_PWM0,
-};
-
-/* GRF_GPIO1A_IOMUX */
-enum {
- GPIO1A7_SHIFT = 14,
- GPIO1A7_MASK = 1,
- GPIO1A7_GPIO = 0,
- GPIO1A7_SDMMC_WRPRT,
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
- GPIO1B7_GPIO = 0,
- GPIO1B7_SDMMC_CMD,
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
- GPIO1B6_GPIO = 0,
- GPIO1B6_SDMMC_PWREN,
-
- GPIO1B4_SHIFT = 8,
- GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
- GPIO1B4_GPIO = 0,
- GPIO1B4_SPI_CSN1,
- GPIO1B4_PWM12,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
- GPIO1B3_GPIO = 0,
- GPIO1B3_UART1_RSTN,
- GPIO1B3_PWM13,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO = 0,
- GPIO1B2_UART1_SIN,
- GPIO1B2_UART21_SIN,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO = 0,
- GPIO1B1_UART1_SOUT,
- GPIO1B1_UART21_SOUT,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C7_SHIFT = 14,
- GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
- GPIO1C7_GPIO = 0,
- GPIO1C7_NAND_CS3,
- GPIO1C7_EMMC_RSTNOUT,
-
- GPIO1C6_SHIFT = 12,
- GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
- GPIO1C6_GPIO = 0,
- GPIO1C6_NAND_CS2,
- GPIO1C6_EMMC_CMD,
-
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
- GPIO1C5_GPIO = 0,
- GPIO1C5_SDMMC_D3,
- GPIO1C5_JTAG_TMS,
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
- GPIO1C4_GPIO = 0,
- GPIO1C4_SDMMC_D2,
- GPIO1C4_JTAG_TCK,
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
- GPIO1C3_GPIO = 0,
- GPIO1C3_SDMMC_D1,
- GPIO1C3_UART2_SIN,
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
- GPIO1C2_GPIO = 0,
- GPIO1C2_SDMMC_D0,
- GPIO1C2_UART2_SOUT,
-
- GPIO1C1_SHIFT = 2,
- GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
- GPIO1C1_GPIO = 0,
- GPIO1C1_SDMMC_DETN,
-
- GPIO1C0_SHIFT = 0,
- GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
- GPIO1C0_GPIO = 0,
- GPIO1C0_SDMMC_CLKOUT,
-};
-
-/* GRF_GPIO1D_IOMUX */
-enum {
- GPIO1D7_SHIFT = 14,
- GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
- GPIO1D7_GPIO = 0,
- GPIO1D7_NAND_D7,
- GPIO1D7_EMMC_D7,
-
- GPIO1D6_SHIFT = 12,
- GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
- GPIO1D6_GPIO = 0,
- GPIO1D6_NAND_D6,
- GPIO1D6_EMMC_D6,
-
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
- GPIO1D5_GPIO = 0,
- GPIO1D5_NAND_D5,
- GPIO1D5_EMMC_D5,
-
- GPIO1D4_SHIFT = 8,
- GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
- GPIO1D4_GPIO = 0,
- GPIO1D4_NAND_D4,
- GPIO1D4_EMMC_D4,
-
- GPIO1D3_SHIFT = 6,
- GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
- GPIO1D3_GPIO = 0,
- GPIO1D3_NAND_D3,
- GPIO1D3_EMMC_D3,
-
- GPIO1D2_SHIFT = 4,
- GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
- GPIO1D2_GPIO = 0,
- GPIO1D2_NAND_D2,
- GPIO1D2_EMMC_D2,
-
- GPIO1D1_SHIFT = 2,
- GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
- GPIO1D1_GPIO = 0,
- GPIO1D1_NAND_D1,
- GPIO1D1_EMMC_D1,
-
- GPIO1D0_SHIFT = 0,
- GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
- GPIO1D0_GPIO = 0,
- GPIO1D0_NAND_D0,
- GPIO1D0_EMMC_D0,
-};
-
-/* GRF_GPIO2A_IOMUX */
-enum {
- GPIO2A7_SHIFT = 14,
- GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
- GPIO2A7_GPIO = 0,
- GPIO2A7_NAND_DQS,
- GPIO2A7_EMMC_CLKOUT,
-
- GPIO2A5_SHIFT = 10,
- GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
- GPIO2A5_GPIO = 0,
- GPIO2A5_NAND_WP,
- GPIO2A5_EMMC_PWREN,
-
- GPIO2A4_SHIFT = 8,
- GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
- GPIO2A4_GPIO = 0,
- GPIO2A4_NAND_RDY,
- GPIO2A4_EMMC_CMD,
-
- GPIO2A3_SHIFT = 6,
- GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
- GPIO2A3_GPIO = 0,
- GPIO2A3_NAND_RDN,
- GPIO2A4_SPI1_CSN1,
-
- GPIO2A2_SHIFT = 4,
- GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
- GPIO2A2_GPIO = 0,
- GPIO2A2_NAND_WRN,
- GPIO2A4_SPI1_CSN0,
-
- GPIO2A1_SHIFT = 2,
- GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
- GPIO2A1_GPIO = 0,
- GPIO2A1_NAND_CLE,
- GPIO2A1_SPI1_TXD,
-
- GPIO2A0_SHIFT = 0,
- GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
- GPIO2A0_GPIO = 0,
- GPIO2A0_NAND_ALE,
- GPIO2A0_SPI1_RXD,
-};
-
-/* GRF_GPIO2B_IOMUX */
-enum {
- GPIO2B7_SHIFT = 14,
- GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
- GPIO2B7_GPIO = 0,
- GPIO2B7_GMAC_RXER,
-
- GPIO2B6_SHIFT = 12,
- GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
- GPIO2B6_GPIO = 0,
- GPIO2B6_GMAC_CLK,
- GPIO2B6_MAC_LINK,
-
- GPIO2B5_SHIFT = 10,
- GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
- GPIO2B5_GPIO = 0,
- GPIO2B5_GMAC_TXEN,
-
- GPIO2B4_SHIFT = 8,
- GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
- GPIO2B4_GPIO = 0,
- GPIO2B4_GMAC_MDIO,
-
- GPIO2B3_SHIFT = 6,
- GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
- GPIO2B3_GPIO = 0,
- GPIO2B3_GMAC_RXCLK,
-
- GPIO2B2_SHIFT = 4,
- GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
- GPIO2B2_GPIO = 0,
- GPIO2B2_GMAC_CRS,
-
- GPIO2B1_SHIFT = 2,
- GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
- GPIO2B1_GPIO = 0,
- GPIO2B1_GMAC_TXCLK,
-
- GPIO2B0_SHIFT = 0,
- GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
- GPIO2B0_GPIO = 0,
- GPIO2B0_GMAC_RXDV,
- GPIO2B0_MAC_SPEED_IOUT,
-};
-
-/* GRF_GPIO2C_IOMUX */
-enum {
- GPIO2C7_SHIFT = 14,
- GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
- GPIO2C7_GPIO = 0,
- GPIO2C7_GMAC_TXD3,
-
- GPIO2C6_SHIFT = 12,
- GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
- GPIO2C6_GPIO = 0,
- GPIO2C6_GMAC_TXD2,
-
- GPIO2C5_SHIFT = 10,
- GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
- GPIO2C5_GPIO = 0,
- GPIO2C5_I2C2_SCL,
- GPIO2C5_GMAC_RXD2,
-
- GPIO2C4_SHIFT = 8,
- GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
- GPIO2C4_GPIO = 0,
- GPIO2C4_I2C2_SDA,
- GPIO2C4_GMAC_RXD3,
-
- GPIO2C3_SHIFT = 6,
- GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
- GPIO2C3_GPIO = 0,
- GPIO2C3_GMAC_TXD0,
-
- GPIO2C2_SHIFT = 4,
- GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
- GPIO2C2_GPIO = 0,
- GPIO2C2_GMAC_TXD1,
-
- GPIO2C1_SHIFT = 2,
- GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
- GPIO2C1_GPIO = 0,
- GPIO2C1_GMAC_RXD0,
-
- GPIO2C0_SHIFT = 0,
- GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
- GPIO2C0_GPIO = 0,
- GPIO2C0_GMAC_RXD1,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
- GPIO2D1_SHIFT = 2,
- GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
- GPIO2D1_GPIO = 0,
- GPIO2D1_GMAC_MDC,
-
- GPIO2D0_SHIFT = 0,
- GPIO2D0_MASK = 3,
- GPIO2D0_GPIO = 0,
- GPIO2D0_GMAC_COL,
-};
-
-/* GRF_GPIO3C_IOMUX */
-enum {
- GPIO3C6_SHIFT = 12,
- GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
- GPIO3C6_GPIO = 0,
- GPIO3C6_DRV_VBUS1,
-
- GPIO3C5_SHIFT = 10,
- GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
- GPIO3C5_GPIO = 0,
- GPIO3C5_PWM10,
-
- GPIO3C1_SHIFT = 2,
- GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
- GPIO3C1_GPIO = 0,
- GPIO3C1_DRV_VBUS,
-};
-
-/* GRF_GPIO3D_IOMUX */
-enum {
- GPIO3D2_SHIFT = 4,
- GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
- GPIO3D2_GPIO = 0,
- GPIO3D2_PWM3,
-};
-
-/* GRF_CON_IOMUX */
-enum {
- CON_IOMUX_GMACSEL_SHIFT = 15,
- CON_IOMUX_GMACSEL_MASK = 1 << CON_IOMUX_GMACSEL_SHIFT,
- CON_IOMUX_GMACSEL_1 = 1,
- CON_IOMUX_UART1SEL_SHIFT = 11,
- CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
- CON_IOMUX_UART2SEL_SHIFT = 8,
- CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
- CON_IOMUX_UART2SEL_2 = 0,
- CON_IOMUX_UART2SEL_21,
- CON_IOMUX_EMMCSEL_SHIFT = 7,
- CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
- CON_IOMUX_PWM3SEL_SHIFT = 3,
- CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
- CON_IOMUX_PWM2SEL_SHIFT = 2,
- CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
- CON_IOMUX_PWM1SEL_SHIFT = 1,
- CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
- CON_IOMUX_PWM0SEL_SHIFT = 0,
- CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
-};
-
-/* GRF_GPIO2B_E */
-enum {
- GRF_GPIO2B0_E_SHIFT = 0,
- GRF_GPIO2B0_E_MASK = 3 << GRF_GPIO2B0_E_SHIFT,
- GRF_GPIO2B1_E_SHIFT = 2,
- GRF_GPIO2B1_E_MASK = 3 << GRF_GPIO2B1_E_SHIFT,
- GRF_GPIO2B3_E_SHIFT = 6,
- GRF_GPIO2B3_E_MASK = 3 << GRF_GPIO2B3_E_SHIFT,
- GRF_GPIO2B4_E_SHIFT = 8,
- GRF_GPIO2B4_E_MASK = 3 << GRF_GPIO2B4_E_SHIFT,
- GRF_GPIO2B5_E_SHIFT = 10,
- GRF_GPIO2B5_E_MASK = 3 << GRF_GPIO2B5_E_SHIFT,
- GRF_GPIO2B6_E_SHIFT = 12,
- GRF_GPIO2B6_E_MASK = 3 << GRF_GPIO2B6_E_SHIFT,
-};
-
-/* GRF_GPIO2C_E */
-enum {
- GRF_GPIO2C0_E_SHIFT = 0,
- GRF_GPIO2C0_E_MASK = 3 << GRF_GPIO2C0_E_SHIFT,
- GRF_GPIO2C1_E_SHIFT = 2,
- GRF_GPIO2C1_E_MASK = 3 << GRF_GPIO2C1_E_SHIFT,
- GRF_GPIO2C2_E_SHIFT = 4,
- GRF_GPIO2C2_E_MASK = 3 << GRF_GPIO2C2_E_SHIFT,
- GRF_GPIO2C3_E_SHIFT = 6,
- GRF_GPIO2C3_E_MASK = 3 << GRF_GPIO2C3_E_SHIFT,
- GRF_GPIO2C4_E_SHIFT = 8,
- GRF_GPIO2C4_E_MASK = 3 << GRF_GPIO2C4_E_SHIFT,
- GRF_GPIO2C5_E_SHIFT = 10,
- GRF_GPIO2C5_E_MASK = 3 << GRF_GPIO2C5_E_SHIFT,
- GRF_GPIO2C6_E_SHIFT = 12,
- GRF_GPIO2C6_E_MASK = 3 << GRF_GPIO2C6_E_SHIFT,
- GRF_GPIO2C7_E_SHIFT = 14,
- GRF_GPIO2C7_E_MASK = 3 << GRF_GPIO2C7_E_SHIFT,
-};
-
-/* GRF_GPIO2D_E */
-enum {
- GRF_GPIO2D1_E_SHIFT = 2,
- GRF_GPIO2D1_E_MASK = 3 << GRF_GPIO2D1_E_SHIFT,
-};
-
-/* GPIO Bias drive strength settings */
-enum GPIO_BIAS {
- GPIO_BIAS_2MA = 0,
- GPIO_BIAS_4MA,
- GPIO_BIAS_8MA,
- GPIO_BIAS_12MA,
-};
-
-struct rk322x_pinctrl_priv {
- struct rk322x_grf *grf;
-};
-
-static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id)
-{
- u32 mux_con = readl(&grf->con_iomux);
-
- switch (pwm_id) {
- case PERIPH_ID_PWM0:
- if (mux_con & CON_IOMUX_PWM0SEL_MASK)
- rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK,
- GPIO3C5_PWM10 << GPIO3C5_SHIFT);
- else
- rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
- GPIO0D2_PWM0 << GPIO0D2_SHIFT);
- break;
- case PERIPH_ID_PWM1:
- if (mux_con & CON_IOMUX_PWM1SEL_MASK)
- rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK,
- GPIO0D6_PWM11 << GPIO0D6_SHIFT);
- else
- rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK,
- GPIO0D3_PWM1 << GPIO0D3_SHIFT);
- break;
- case PERIPH_ID_PWM2:
- if (mux_con & CON_IOMUX_PWM2SEL_MASK)
- rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
- GPIO1B4_PWM12 << GPIO1B4_SHIFT);
- else
- rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK,
- GPIO0D4_PWM2 << GPIO0D4_SHIFT);
- break;
- case PERIPH_ID_PWM3:
- if (mux_con & CON_IOMUX_PWM3SEL_MASK)
- rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK,
- GPIO1B3_PWM13 << GPIO1B3_SHIFT);
- else
- rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK,
- GPIO3D2_PWM3 << GPIO3D2_SHIFT);
- break;
- default:
- debug("pwm id = %d iomux error!\n", pwm_id);
- break;
- }
-}
-
-static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id)
-{
- switch (i2c_id) {
- case PERIPH_ID_I2C0:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A1_MASK | GPIO0A0_MASK,
- GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
- GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
-
- break;
- case PERIPH_ID_I2C1:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A3_MASK | GPIO0A2_MASK,
- GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
- GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
- break;
- case PERIPH_ID_I2C2:
- rk_clrsetreg(&grf->gpio2c_iomux,
- GPIO2C5_MASK | GPIO2C4_MASK,
- GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
- GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
- break;
- case PERIPH_ID_I2C3:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A7_MASK | GPIO0A6_MASK,
- GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
- GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
-
- break;
- }
-}
-
-static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs)
-{
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK,
- GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
- GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT);
- break;
- }
- rk_clrsetreg(&grf->gpio0b_iomux,
- GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK,
- GPIO0B5_SPI_RXD << GPIO0B5_SHIFT |
- GPIO0B3_SPI_TXD << GPIO0B3_SHIFT |
- GPIO0B1_SPI_CLK << GPIO0B1_SHIFT);
-}
-
-static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id)
-{
- u32 mux_con = readl(&grf->con_iomux);
-
- switch (uart_id) {
- case PERIPH_ID_UART1:
- if (!(mux_con & CON_IOMUX_UART1SEL_MASK))
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B1_MASK | GPIO1B2_MASK,
- GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT |
- GPIO1B2_UART1_SIN << GPIO1B2_SHIFT);
- break;
- case PERIPH_ID_UART2:
- if (mux_con & CON_IOMUX_UART2SEL_MASK)
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B1_MASK | GPIO1B2_MASK,
- GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT |
- GPIO1B2_UART21_SIN << GPIO1B2_SHIFT);
- else
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C3_MASK | GPIO1C2_MASK,
- GPIO1C3_UART2_SIN << GPIO1C3_SHIFT |
- GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT);
- break;
- }
-}
-
-static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
-{
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
- GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
- GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
- GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
- GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
- GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
- GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
- GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
- GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A5_MASK | GPIO2A7_MASK,
- GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
- GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C6_MASK | GPIO1C7_MASK,
- GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT |
- GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT);
- break;
- case PERIPH_ID_SDCARD:
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B6_MASK | GPIO1B7_MASK,
- GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT |
- GPIO1B7_SDMMC_CMD << GPIO1B7_SHIFT);
- rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
- GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT |
- GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT |
- GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT |
- GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT |
- GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT |
- GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT);
- break;
- }
-}
-
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
-static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id)
-{
- switch (gmac_id) {
- case PERIPH_ID_GMAC:
- /* set rgmii pins mux */
- rk_clrsetreg(&grf->gpio2b_iomux,
- GPIO2B0_MASK |
- GPIO2B1_MASK |
- GPIO2B3_MASK |
- GPIO2B4_MASK |
- GPIO2B5_MASK |
- GPIO2B6_MASK,
- GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT |
- GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT |
- GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT |
- GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT |
- GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT |
- GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT);
-
- rk_clrsetreg(&grf->gpio2c_iomux,
- GPIO2C0_MASK |
- GPIO2C1_MASK |
- GPIO2C2_MASK |
- GPIO2C3_MASK |
- GPIO2C4_MASK |
- GPIO2C5_MASK |
- GPIO2C6_MASK |
- GPIO2C7_MASK,
- GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT |
- GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT |
- GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT |
- GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT |
- GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT |
- GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT |
- GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT |
- GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT);
-
- rk_clrsetreg(&grf->gpio2d_iomux,
- GPIO2D1_MASK,
- GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT);
-
- /*
- * set rgmii tx pins to 12ma drive-strength,
- * clean others with 2ma.
- */
- rk_clrsetreg(&grf->gpio2_e[1],
- GRF_GPIO2B0_E_MASK |
- GRF_GPIO2B1_E_MASK |
- GRF_GPIO2B3_E_MASK |
- GRF_GPIO2B4_E_MASK |
- GRF_GPIO2B5_E_MASK |
- GRF_GPIO2B6_E_MASK,
- GPIO_BIAS_2MA << GRF_GPIO2B0_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO2B1_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO2B3_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO2B4_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO2B5_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO2B6_E_SHIFT);
-
- rk_clrsetreg(&grf->gpio2_e[2],
- GRF_GPIO2C0_E_MASK |
- GRF_GPIO2C1_E_MASK |
- GRF_GPIO2C2_E_MASK |
- GRF_GPIO2C3_E_MASK |
- GRF_GPIO2C4_E_MASK |
- GRF_GPIO2C5_E_MASK |
- GRF_GPIO2C6_E_MASK |
- GRF_GPIO2C7_E_MASK,
- GPIO_BIAS_2MA << GRF_GPIO2C0_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO2C1_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO2C2_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO2C3_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO2C4_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO2C5_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO2C6_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO2C7_E_SHIFT);
-
- rk_clrsetreg(&grf->gpio2_e[3],
- GRF_GPIO2D1_E_MASK,
- GPIO_BIAS_2MA << GRF_GPIO2D1_E_SHIFT);
- break;
- default:
- debug("gmac id = %d iomux error!\n", gmac_id);
- break;
- }
-}
-#endif
-
-static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%x, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- pinctrl_rk322x_pwm_config(priv->grf, func);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- pinctrl_rk322x_i2c_config(priv->grf, func);
- break;
- case PERIPH_ID_SPI0:
- pinctrl_rk322x_spi_config(priv->grf, flags);
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- pinctrl_rk322x_uart_config(priv->grf, func);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- pinctrl_rk322x_sdmmc_config(priv->grf, func);
- break;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case PERIPH_ID_GMAC:
- pinctrl_rk322x_gmac_config(priv->grf, func);
- break;
-#endif
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk322x_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
- u32 cell[3];
- int ret;
-
- ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
- "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 12:
- return PERIPH_ID_SDCARD;
- case 14:
- return PERIPH_ID_EMMC;
- case 36:
- return PERIPH_ID_I2C0;
- case 37:
- return PERIPH_ID_I2C1;
- case 38:
- return PERIPH_ID_I2C2;
- case 49:
- return PERIPH_ID_SPI0;
- case 50:
- return PERIPH_ID_PWM0;
- case 55:
- return PERIPH_ID_UART0;
- case 56:
- return PERIPH_ID_UART1;
- case 57:
- return PERIPH_ID_UART2;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case 24:
- return PERIPH_ID_GMAC;
-#endif
- }
- return -ENOENT;
-}
-
-static int rk322x_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk322x_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
- return rk322x_pinctrl_request(dev, func, 0);
-}
-
-static struct pinctrl_ops rk322x_pinctrl_ops = {
- .set_state_simple = rk322x_pinctrl_set_state_simple,
- .request = rk322x_pinctrl_request,
- .get_periph_id = rk322x_pinctrl_get_periph_id,
-};
-
-static int rk322x_pinctrl_probe(struct udevice *dev)
-{
- struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- debug("%s: grf=%p\n", __func__, priv->grf);
- return 0;
-}
-
-static const struct udevice_id rk322x_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3228-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3228) = {
- .name = "pinctrl_rk3228",
- .id = UCLASS_PINCTRL,
- .of_match = rk322x_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),
- .ops = &rk322x_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
- .probe = rk322x_pinctrl_probe,
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Pinctrl driver for Rockchip SoCs
- * Copyright (c) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3288.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct rk3288_pinctrl_priv {
- struct rk3288_grf *grf;
- struct rk3288_pmu *pmu;
- int num_banks;
-};
-
-/**
- * Encode variants of iomux registers into a type variable
- */
-#define IOMUX_GPIO_ONLY BIT(0)
-#define IOMUX_WIDTH_4BIT BIT(1)
-#define IOMUX_SOURCE_PMU BIT(2)
-#define IOMUX_UNROUTED BIT(3)
-
-/**
- * @type: iomux variant using IOMUX_* constants
- * @offset: if initialized to -1 it will be autocalculated, by specifying
- * an initial offset value the relevant source offset can be reset
- * to a new value for autocalculating the following iomux registers.
- */
-struct rockchip_iomux {
- u8 type;
- s16 offset;
-};
-
-/**
- * @reg: register offset of the gpio bank
- * @nr_pins: number of pins in this bank
- * @bank_num: number of the bank, to account for holes
- * @name: name of the bank
- * @iomux: array describing the 4 iomux sources of the bank
- */
-struct rockchip_pin_bank {
- u16 reg;
- u8 nr_pins;
- u8 bank_num;
- char *name;
- struct rockchip_iomux iomux[4];
-};
-
-#define PIN_BANK(id, pins, label) \
- { \
- .bank_num = id, \
- .nr_pins = pins, \
- .name = label, \
- .iomux = { \
- { .offset = -1 }, \
- { .offset = -1 }, \
- { .offset = -1 }, \
- { .offset = -1 }, \
- }, \
- }
-
-#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
- { \
- .bank_num = id, \
- .nr_pins = pins, \
- .name = label, \
- .iomux = { \
- { .type = iom0, .offset = -1 }, \
- { .type = iom1, .offset = -1 }, \
- { .type = iom2, .offset = -1 }, \
- { .type = iom3, .offset = -1 }, \
- }, \
- }
-
-#ifndef CONFIG_SPL_BUILD
-static struct rockchip_pin_bank rk3288_pin_banks[] = {
- PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
- IOMUX_SOURCE_PMU,
- IOMUX_SOURCE_PMU,
- IOMUX_UNROUTED
- ),
- PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
- IOMUX_UNROUTED,
- IOMUX_UNROUTED,
- 0
- ),
- PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
- PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
- PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
- IOMUX_WIDTH_4BIT,
- 0,
- 0
- ),
- PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
- 0,
- 0,
- IOMUX_UNROUTED
- ),
- PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
- PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
- 0,
- IOMUX_WIDTH_4BIT,
- IOMUX_UNROUTED
- ),
- PIN_BANK(8, 16, "gpio8"),
-};
-#endif
-
-static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id)
-{
- switch (pwm_id) {
- case PERIPH_ID_PWM0:
- rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A0_MASK << GPIO7A0_SHIFT,
- GPIO7A0_PWM_0 << GPIO7A0_SHIFT);
- break;
- case PERIPH_ID_PWM1:
- rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A1_MASK << GPIO7A1_SHIFT,
- GPIO7A1_PWM_1 << GPIO7A1_SHIFT);
- break;
- case PERIPH_ID_PWM2:
- rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C6_MASK << GPIO7C6_SHIFT,
- GPIO7C6_PWM_2 << GPIO7C6_SHIFT);
- break;
- case PERIPH_ID_PWM3:
- rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C7_MASK << GPIO7C6_SHIFT,
- GPIO7C7_PWM_3 << GPIO7C7_SHIFT);
- break;
- default:
- debug("pwm id = %d iomux error!\n", pwm_id);
- break;
- }
-}
-
-static void pinctrl_rk3288_i2c_config(struct rk3288_grf *grf,
- struct rk3288_pmu *pmu, int i2c_id)
-{
- switch (i2c_id) {
- case PERIPH_ID_I2C0:
- clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_B],
- GPIO0_B7_MASK << GPIO0_B7_SHIFT,
- GPIO0_B7_I2C0PMU_SDA << GPIO0_B7_SHIFT);
- clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_C],
- GPIO0_C0_MASK << GPIO0_C0_SHIFT,
- GPIO0_C0_I2C0PMU_SCL << GPIO0_C0_SHIFT);
- break;
-#ifndef CONFIG_SPL_BUILD
- case PERIPH_ID_I2C1:
- rk_clrsetreg(&grf->gpio8a_iomux,
- GPIO8A4_MASK << GPIO8A4_SHIFT |
- GPIO8A5_MASK << GPIO8A5_SHIFT,
- GPIO8A4_I2C2SENSOR_SDA << GPIO8A4_SHIFT |
- GPIO8A5_I2C2SENSOR_SCL << GPIO8A5_SHIFT);
- break;
- case PERIPH_ID_I2C2:
- rk_clrsetreg(&grf->gpio6b_iomux,
- GPIO6B1_MASK << GPIO6B1_SHIFT |
- GPIO6B2_MASK << GPIO6B2_SHIFT,
- GPIO6B1_I2C1AUDIO_SDA << GPIO6B1_SHIFT |
- GPIO6B2_I2C1AUDIO_SCL << GPIO6B2_SHIFT);
- break;
- case PERIPH_ID_I2C3:
- rk_clrsetreg(&grf->gpio2c_iomux,
- GPIO2C1_MASK << GPIO2C1_SHIFT |
- GPIO2C0_MASK << GPIO2C0_SHIFT,
- GPIO2C1_I2C3CAM_SDA << GPIO2C1_SHIFT |
- GPIO2C0_I2C3CAM_SCL << GPIO2C0_SHIFT);
- break;
- case PERIPH_ID_I2C4:
- rk_clrsetreg(&grf->gpio7cl_iomux,
- GPIO7C1_MASK << GPIO7C1_SHIFT |
- GPIO7C2_MASK << GPIO7C2_SHIFT,
- GPIO7C1_I2C4TP_SDA << GPIO7C1_SHIFT |
- GPIO7C2_I2C4TP_SCL << GPIO7C2_SHIFT);
- break;
- case PERIPH_ID_I2C5:
- rk_clrsetreg(&grf->gpio7cl_iomux,
- GPIO7C3_MASK << GPIO7C3_SHIFT,
- GPIO7C3_I2C5HDMI_SDA << GPIO7C3_SHIFT);
- rk_clrsetreg(&grf->gpio7ch_iomux,
- GPIO7C4_MASK << GPIO7C4_SHIFT,
- GPIO7C4_I2C5HDMI_SCL << GPIO7C4_SHIFT);
- break;
-#endif
- default:
- debug("i2c id = %d iomux error!\n", i2c_id);
- break;
- }
-}
-
-#ifndef CONFIG_SPL_BUILD
-static void pinctrl_rk3288_lcdc_config(struct rk3288_grf *grf, int lcd_id)
-{
- switch (lcd_id) {
- case PERIPH_ID_LCDC0:
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D3_MASK << GPIO1D0_SHIFT |
- GPIO1D2_MASK << GPIO1D2_SHIFT |
- GPIO1D1_MASK << GPIO1D1_SHIFT |
- GPIO1D0_MASK << GPIO1D0_SHIFT,
- GPIO1D3_LCDC0_DCLK << GPIO1D3_SHIFT |
- GPIO1D2_LCDC0_DEN << GPIO1D2_SHIFT |
- GPIO1D1_LCDC0_VSYNC << GPIO1D1_SHIFT |
- GPIO1D0_LCDC0_HSYNC << GPIO1D0_SHIFT);
- break;
- default:
- debug("lcdc id = %d iomux error!\n", lcd_id);
- break;
- }
-}
-#endif
-
-static int pinctrl_rk3288_spi_config(struct rk3288_grf *grf,
- enum periph_id spi_id, int cs)
-{
- switch (spi_id) {
-#ifndef CONFIG_SPL_BUILD
- case PERIPH_ID_SPI0:
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio5b_iomux,
- GPIO5B5_MASK << GPIO5B5_SHIFT,
- GPIO5B5_SPI0_CSN0 << GPIO5B5_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio5c_iomux,
- GPIO5C0_MASK << GPIO5C0_SHIFT,
- GPIO5C0_SPI0_CSN1 << GPIO5C0_SHIFT);
- break;
- default:
- goto err;
- }
- rk_clrsetreg(&grf->gpio5b_iomux,
- GPIO5B7_MASK << GPIO5B7_SHIFT |
- GPIO5B6_MASK << GPIO5B6_SHIFT |
- GPIO5B4_MASK << GPIO5B4_SHIFT,
- GPIO5B7_SPI0_RXD << GPIO5B7_SHIFT |
- GPIO5B6_SPI0_TXD << GPIO5B6_SHIFT |
- GPIO5B4_SPI0_CLK << GPIO5B4_SHIFT);
- break;
- case PERIPH_ID_SPI1:
- if (cs != 0)
- goto err;
- rk_clrsetreg(&grf->gpio7b_iomux,
- GPIO7B6_MASK << GPIO7B6_SHIFT |
- GPIO7B7_MASK << GPIO7B7_SHIFT |
- GPIO7B5_MASK << GPIO7B5_SHIFT |
- GPIO7B4_MASK << GPIO7B4_SHIFT,
- GPIO7B6_SPI1_RXD << GPIO7B6_SHIFT |
- GPIO7B7_SPI1_TXD << GPIO7B7_SHIFT |
- GPIO7B5_SPI1_CSN0 << GPIO7B5_SHIFT |
- GPIO7B4_SPI1_CLK << GPIO7B4_SHIFT);
- break;
-#endif
- case PERIPH_ID_SPI2:
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio8a_iomux,
- GPIO8A7_MASK << GPIO8A7_SHIFT,
- GPIO8A7_SPI2_CSN0 << GPIO8A7_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio8a_iomux,
- GPIO8A3_MASK << GPIO8A3_SHIFT,
- GPIO8A3_SPI2_CSN1 << GPIO8A3_SHIFT);
- break;
- default:
- goto err;
- }
- rk_clrsetreg(&grf->gpio8b_iomux,
- GPIO8B1_MASK << GPIO8B1_SHIFT |
- GPIO8B0_MASK << GPIO8B0_SHIFT,
- GPIO8B1_SPI2_TXD << GPIO8B1_SHIFT |
- GPIO8B0_SPI2_RXD << GPIO8B0_SHIFT);
- rk_clrsetreg(&grf->gpio8a_iomux,
- GPIO8A6_MASK << GPIO8A6_SHIFT,
- GPIO8A6_SPI2_CLK << GPIO8A6_SHIFT);
- break;
- default:
- goto err;
- }
-
- return 0;
-err:
- debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
- return -ENOENT;
-}
-
-static void pinctrl_rk3288_uart_config(struct rk3288_grf *grf, int uart_id)
-{
- switch (uart_id) {
-#ifndef CONFIG_SPL_BUILD
- case PERIPH_ID_UART_BT:
- rk_clrsetreg(&grf->gpio4c_iomux,
- GPIO4C3_MASK << GPIO4C3_SHIFT |
- GPIO4C2_MASK << GPIO4C2_SHIFT |
- GPIO4C1_MASK << GPIO4C1_SHIFT |
- GPIO4C0_MASK << GPIO4C0_SHIFT,
- GPIO4C3_UART0BT_RTSN << GPIO4C3_SHIFT |
- GPIO4C2_UART0BT_CTSN << GPIO4C2_SHIFT |
- GPIO4C1_UART0BT_SOUT << GPIO4C1_SHIFT |
- GPIO4C0_UART0BT_SIN << GPIO4C0_SHIFT);
- break;
- case PERIPH_ID_UART_BB:
- rk_clrsetreg(&grf->gpio5b_iomux,
- GPIO5B3_MASK << GPIO5B3_SHIFT |
- GPIO5B2_MASK << GPIO5B2_SHIFT |
- GPIO5B1_MASK << GPIO5B1_SHIFT |
- GPIO5B0_MASK << GPIO5B0_SHIFT,
- GPIO5B3_UART1BB_RTSN << GPIO5B3_SHIFT |
- GPIO5B2_UART1BB_CTSN << GPIO5B2_SHIFT |
- GPIO5B1_UART1BB_SOUT << GPIO5B1_SHIFT |
- GPIO5B0_UART1BB_SIN << GPIO5B0_SHIFT);
- break;
-#endif
- case PERIPH_ID_UART_DBG:
- rk_clrsetreg(&grf->gpio7ch_iomux,
- GPIO7C7_MASK << GPIO7C7_SHIFT |
- GPIO7C6_MASK << GPIO7C6_SHIFT,
- GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
- GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
- break;
-#ifndef CONFIG_SPL_BUILD
- case PERIPH_ID_UART_GPS:
- rk_clrsetreg(&grf->gpio7b_iomux,
- GPIO7B2_MASK << GPIO7B2_SHIFT |
- GPIO7B1_MASK << GPIO7B1_SHIFT |
- GPIO7B0_MASK << GPIO7B0_SHIFT,
- GPIO7B2_UART3GPS_RTSN << GPIO7B2_SHIFT |
- GPIO7B1_UART3GPS_CTSN << GPIO7B1_SHIFT |
- GPIO7B0_UART3GPS_SOUT << GPIO7B0_SHIFT);
- rk_clrsetreg(&grf->gpio7a_iomux,
- GPIO7A7_MASK << GPIO7A7_SHIFT,
- GPIO7A7_UART3GPS_SIN << GPIO7A7_SHIFT);
- break;
- case PERIPH_ID_UART_EXP:
- rk_clrsetreg(&grf->gpio5b_iomux,
- GPIO5B5_MASK << GPIO5B5_SHIFT |
- GPIO5B4_MASK << GPIO5B4_SHIFT |
- GPIO5B6_MASK << GPIO5B6_SHIFT |
- GPIO5B7_MASK << GPIO5B7_SHIFT,
- GPIO5B5_UART4EXP_RTSN << GPIO5B5_SHIFT |
- GPIO5B4_UART4EXP_CTSN << GPIO5B4_SHIFT |
- GPIO5B6_UART4EXP_SOUT << GPIO5B6_SHIFT |
- GPIO5B7_UART4EXP_SIN << GPIO5B7_SHIFT);
- break;
-#endif
- default:
- debug("uart id = %d iomux error!\n", uart_id);
- break;
- }
-}
-
-static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf *grf, int mmc_id)
-{
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- rk_clrsetreg(&grf->gpio3a_iomux, 0xffff,
- GPIO3A7_EMMC_DATA7 << GPIO3A7_SHIFT |
- GPIO3A6_EMMC_DATA6 << GPIO3A6_SHIFT |
- GPIO3A5_EMMC_DATA5 << GPIO3A5_SHIFT |
- GPIO3A4_EMMC_DATA4 << GPIO3A4_SHIFT |
- GPIO3A3_EMMC_DATA3 << GPIO3A3_SHIFT |
- GPIO3A2_EMMC_DATA2 << GPIO3A2_SHIFT |
- GPIO3A1_EMMC_DATA1 << GPIO3A1_SHIFT |
- GPIO3A0_EMMC_DATA0 << GPIO3A0_SHIFT);
- rk_clrsetreg(&grf->gpio3b_iomux, GPIO3B1_MASK << GPIO3B1_SHIFT,
- GPIO3B1_EMMC_PWREN << GPIO3B1_SHIFT);
- rk_clrsetreg(&grf->gpio3c_iomux,
- GPIO3C0_MASK << GPIO3C0_SHIFT,
- GPIO3C0_EMMC_CMD << GPIO3C0_SHIFT);
- break;
- case PERIPH_ID_SDCARD:
- rk_clrsetreg(&grf->gpio6c_iomux, 0xffff,
- GPIO6C6_SDMMC0_DECTN << GPIO6C6_SHIFT |
- GPIO6C5_SDMMC0_CMD << GPIO6C5_SHIFT |
- GPIO6C4_SDMMC0_CLKOUT << GPIO6C4_SHIFT |
- GPIO6C3_SDMMC0_DATA3 << GPIO6C3_SHIFT |
- GPIO6C2_SDMMC0_DATA2 << GPIO6C2_SHIFT |
- GPIO6C1_SDMMC0_DATA1 << GPIO6C1_SHIFT |
- GPIO6C0_SDMMC0_DATA0 << GPIO6C0_SHIFT);
-
- /* use sdmmc0 io, disable JTAG function */
- rk_clrsetreg(&grf->soc_con0, 1 << GRF_FORCE_JTAG_SHIFT, 0);
- break;
- default:
- debug("mmc id = %d iomux error!\n", mmc_id);
- break;
- }
-}
-
-static void pinctrl_rk3288_gmac_config(struct rk3288_grf *grf, int gmac_id)
-{
- switch (gmac_id) {
- case PERIPH_ID_GMAC:
- rk_clrsetreg(&grf->gpio3dl_iomux,
- GPIO3D3_MASK << GPIO3D3_SHIFT |
- GPIO3D2_MASK << GPIO3D2_SHIFT |
- GPIO3D2_MASK << GPIO3D1_SHIFT |
- GPIO3D0_MASK << GPIO3D0_SHIFT,
- GPIO3D3_MAC_RXD3 << GPIO3D3_SHIFT |
- GPIO3D2_MAC_RXD2 << GPIO3D2_SHIFT |
- GPIO3D1_MAC_TXD3 << GPIO3D1_SHIFT |
- GPIO3D0_MAC_TXD2 << GPIO3D0_SHIFT);
-
- rk_clrsetreg(&grf->gpio3dh_iomux,
- GPIO3D7_MASK << GPIO3D7_SHIFT |
- GPIO3D6_MASK << GPIO3D6_SHIFT |
- GPIO3D5_MASK << GPIO3D5_SHIFT |
- GPIO3D4_MASK << GPIO3D4_SHIFT,
- GPIO3D7_MAC_RXD1 << GPIO3D7_SHIFT |
- GPIO3D6_MAC_RXD0 << GPIO3D6_SHIFT |
- GPIO3D5_MAC_TXD1 << GPIO3D5_SHIFT |
- GPIO3D4_MAC_TXD0 << GPIO3D4_SHIFT);
-
- /* switch the Tx pins to 12ma drive-strength */
- rk_clrsetreg(&grf->gpio1_e[2][3],
- GPIO_BIAS_MASK |
- (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1)) |
- (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4)) |
- (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(5)),
- (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(0)) |
- (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1)) |
- (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4)) |
- (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(5)));
-
- /* Set normal pull for all GPIO3D pins */
- rk_clrsetreg(&grf->gpio1_p[2][3],
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)),
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7)));
-
- rk_clrsetreg(&grf->gpio4al_iomux,
- GPIO4A3_MASK << GPIO4A3_SHIFT |
- GPIO4A1_MASK << GPIO4A1_SHIFT |
- GPIO4A0_MASK << GPIO4A0_SHIFT,
- GPIO4A3_MAC_CLK << GPIO4A3_SHIFT |
- GPIO4A1_MAC_TXDV << GPIO4A1_SHIFT |
- GPIO4A0_MAC_MDC << GPIO4A0_SHIFT);
-
- rk_clrsetreg(&grf->gpio4ah_iomux,
- GPIO4A6_MASK << GPIO4A6_SHIFT |
- GPIO4A5_MASK << GPIO4A5_SHIFT |
- GPIO4A4_MASK << GPIO4A4_SHIFT,
- GPIO4A6_MAC_RXCLK << GPIO4A6_SHIFT |
- GPIO4A5_MAC_MDIO << GPIO4A5_SHIFT |
- GPIO4A4_MAC_TXEN << GPIO4A4_SHIFT);
-
- /* switch GPIO4A4 to 12ma drive-strength */
- rk_clrsetreg(&grf->gpio1_e[3][0],
- GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4),
- GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4));
-
- /* Set normal pull for all GPIO4A pins */
- rk_clrsetreg(&grf->gpio1_p[3][0],
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)),
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7)));
-
- rk_clrsetreg(&grf->gpio4bl_iomux,
- GPIO4B1_MASK << GPIO4B1_SHIFT,
- GPIO4B1_MAC_TXCLK << GPIO4B1_SHIFT);
-
- /* switch GPIO4B1 to 12ma drive-strength */
- rk_clrsetreg(&grf->gpio1_e[3][1],
- GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1),
- GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1));
-
- /* Set pull normal for GPIO4B1 */
- rk_clrsetreg(&grf->gpio1_p[3][1],
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)),
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)));
-
- break;
- default:
- printf("gmac id = %d iomux error!\n", gmac_id);
- break;
- }
-}
-
-#ifndef CONFIG_SPL_BUILD
-static void pinctrl_rk3288_hdmi_config(struct rk3288_grf *grf, int hdmi_id)
-{
- switch (hdmi_id) {
- case PERIPH_ID_HDMI:
- rk_clrsetreg(&grf->gpio7cl_iomux, GPIO7C3_MASK << GPIO7C3_SHIFT,
- GPIO7C3_EDPHDMII2C_SDA << GPIO7C3_SHIFT);
- rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C4_MASK << GPIO7C4_SHIFT,
- GPIO7C4_EDPHDMII2C_SCL << GPIO7C4_SHIFT);
- break;
- default:
- debug("hdmi id = %d iomux error!\n", hdmi_id);
- break;
- }
-}
-
-static void pinctrl_rk3288_i2s_config(struct rk3288_grf *grf)
-{
- rk_setreg(&grf->gpio6a_iomux, GPIO6A4_I2S_SDO0 << GPIO6A4_SHIFT |
- GPIO6A3_I2S_SDI << GPIO6A3_SHIFT |
- GPIO6A2_I2S_LRCKTX << GPIO6A2_SHIFT |
- GPIO6A1_I2S_LRCKRX << GPIO6A1_SHIFT |
- GPIO6A0_I2S_SCLK << GPIO6A0_SHIFT);
- rk_setreg(&grf->gpio6b_iomux, GPIO6B0_I2S_CLK << GPIO6B0_SHIFT);
- rk_setreg(&grf->io_vsel, AUDIO_V18SEL_1_8V << AUDIO_V18SEL_SHIFT);
-}
-#endif
-
-static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%x, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- case PERIPH_ID_PWM4:
- pinctrl_rk3288_pwm_config(priv->grf, func);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- pinctrl_rk3288_i2c_config(priv->grf, priv->pmu, func);
- break;
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- case PERIPH_ID_SPI2:
- pinctrl_rk3288_spi_config(priv->grf, func, flags);
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- case PERIPH_ID_UART4:
- pinctrl_rk3288_uart_config(priv->grf, func);
- break;
-#ifndef CONFIG_SPL_BUILD
- case PERIPH_ID_I2S:
- pinctrl_rk3288_i2s_config(priv->grf);
- break;
- case PERIPH_ID_LCDC0:
- case PERIPH_ID_LCDC1:
- pinctrl_rk3288_lcdc_config(priv->grf, func);
- break;
- case PERIPH_ID_HDMI:
- pinctrl_rk3288_hdmi_config(priv->grf, func);
- break;
-#endif
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- pinctrl_rk3288_sdmmc_config(priv->grf, func);
- break;
- case PERIPH_ID_GMAC:
- pinctrl_rk3288_gmac_config(priv->grf, func);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk3288_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- u32 cell[3];
- int ret;
-
- ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 27:
- return PERIPH_ID_GMAC;
- case 44:
- return PERIPH_ID_SPI0;
- case 45:
- return PERIPH_ID_SPI1;
- case 46:
- return PERIPH_ID_SPI2;
- case 60:
- return PERIPH_ID_I2C0;
- case 62: /* Note strange order */
- return PERIPH_ID_I2C1;
- case 61:
- return PERIPH_ID_I2C2;
- case 63:
- return PERIPH_ID_I2C3;
- case 64:
- return PERIPH_ID_I2C4;
- case 65:
- return PERIPH_ID_I2C5;
- case 103:
- return PERIPH_ID_HDMI;
- }
-#endif
-
- return -ENOENT;
-}
-
-static int rk3288_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk3288_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
- return rk3288_pinctrl_request(dev, func, 0);
-}
-
-#ifndef CONFIG_SPL_BUILD
-int rk3288_pinctrl_get_pin_info(struct rk3288_pinctrl_priv *priv,
- int banknum, int ind, u32 **addrp, uint *shiftp,
- uint *maskp)
-{
- struct rockchip_pin_bank *bank = &rk3288_pin_banks[banknum];
- uint muxnum;
- u32 *addr;
-
- for (muxnum = 0; muxnum < 4; muxnum++) {
- struct rockchip_iomux *mux = &bank->iomux[muxnum];
-
- if (ind >= 8) {
- ind -= 8;
- continue;
- }
-
- if (mux->type & IOMUX_SOURCE_PMU)
- addr = priv->pmu->gpio0_iomux;
- else
- addr = (u32 *)priv->grf - 4;
- addr += mux->offset;
- *shiftp = ind & 7;
- if (mux->type & IOMUX_WIDTH_4BIT) {
- *maskp = 0xf;
- *shiftp *= 4;
- if (*shiftp >= 16) {
- *shiftp -= 16;
- addr++;
- }
- } else {
- *maskp = 3;
- *shiftp *= 2;
- }
-
- debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
- *maskp, *shiftp);
- *addrp = addr;
- return 0;
- }
-
- return -EINVAL;
-}
-
-static int rk3288_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
- int index)
-{
- struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
- uint shift;
- uint mask;
- u32 *addr;
- int ret;
-
- ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
- &mask);
- if (ret)
- return ret;
- return (readl(addr) & mask) >> shift;
-}
-
-static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
- int muxval, int flags)
-{
- struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
- uint shift, ind = index;
- uint mask;
- uint value;
- u32 *addr;
- int ret;
-
- debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
- ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
- &mask);
- if (ret)
- return ret;
-
- /*
- * PMU_GPIO0 registers cannot be selectively written so we cannot use
- * rk_clrsetreg() here. However, the upper 16 bits are reserved and
- * are ignored when written, so we can use the same code as for the
- * other GPIO banks providing that we preserve the value of the other
- * bits.
- */
- value = readl(addr);
- value &= ~(mask << shift);
- value |= (mask << (shift + 16)) | (muxval << shift);
- writel(value, addr);
-
- /* Handle pullup/pulldown/drive-strength */
- if (flags) {
- uint val = 0;
-
- if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
- val = 1;
- else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
- val = 2;
- else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH))
- val = 3;
-
- shift = (index & 7) * 2;
- ind = index >> 3;
- if (banknum == 0)
- addr = &priv->pmu->gpio0pull[ind];
- else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH))
- addr = &priv->grf->gpio1_e[banknum - 1][ind];
- else
- addr = &priv->grf->gpio1_p[banknum - 1][ind];
- debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
- shift);
-
- /* As above, rk_clrsetreg() cannot be used here. */
- value = readl(addr);
- value &= ~(mask << shift);
- value |= (3 << (shift + 16)) | (val << shift);
- writel(value, addr);
- }
-
- return 0;
-}
-
-static int rk3288_pinctrl_set_state(struct udevice *dev, struct udevice *config)
-{
- const void *blob = gd->fdt_blob;
- int pcfg_node, ret, flags, count, i;
- u32 cell[60], *ptr;
-
- debug("%s: %s %s\n", __func__, dev->name, config->name);
- ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
- "rockchip,pins", cell,
- ARRAY_SIZE(cell));
- if (ret < 0) {
- debug("%s: bad array %d\n", __func__, ret);
- return -EINVAL;
- }
- count = ret;
- for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
- pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
- if (pcfg_node < 0)
- return -EINVAL;
- flags = pinctrl_decode_pin_config(blob, pcfg_node);
- if (flags < 0)
- return flags;
-
- if (fdtdec_get_int(blob, pcfg_node, "drive-strength", 0) == 12)
- flags |= 1 << PIN_CONFIG_DRIVE_STRENGTH;
-
- ret = rk3288_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
- flags);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
-static struct pinctrl_ops rk3288_pinctrl_ops = {
-#ifndef CONFIG_SPL_BUILD
- .set_state = rk3288_pinctrl_set_state,
- .get_gpio_mux = rk3288_pinctrl_get_gpio_mux,
-#endif
- .set_state_simple = rk3288_pinctrl_set_state_simple,
- .request = rk3288_pinctrl_request,
- .get_periph_id = rk3288_pinctrl_get_periph_id,
-};
-
-#ifndef CONFIG_SPL_BUILD
-static int rk3288_pinctrl_parse_tables(struct rk3288_pinctrl_priv *priv,
- struct rockchip_pin_bank *banks,
- int count)
-{
- struct rockchip_pin_bank *bank;
- uint reg, muxnum, banknum;
-
- reg = 0;
- for (banknum = 0; banknum < count; banknum++) {
- bank = &banks[banknum];
- bank->reg = reg;
- debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
- for (muxnum = 0; muxnum < 4; muxnum++) {
- struct rockchip_iomux *mux = &bank->iomux[muxnum];
-
- if (!(mux->type & IOMUX_UNROUTED))
- mux->offset = reg;
- if (mux->type & IOMUX_WIDTH_4BIT)
- reg += 2;
- else
- reg += 1;
- }
- }
-
- return 0;
-}
-#endif
-
-static int rk3288_pinctrl_probe(struct udevice *dev)
-{
- struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
- int ret = 0;
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
- debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
-#ifndef CONFIG_SPL_BUILD
- ret = rk3288_pinctrl_parse_tables(priv, rk3288_pin_banks,
- ARRAY_SIZE(rk3288_pin_banks));
-#endif
-
- return ret;
-}
-
-static const struct udevice_id rk3288_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3288-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3288) = {
- .name = "rockchip_rk3288_pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = rk3288_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv),
- .ops = &rk3288_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- .bind = dm_scan_fdt_dev,
-#endif
- .probe = rk3288_pinctrl_probe,
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/grf_rk3328.h>
-#include <asm/arch/periph.h>
-#include <asm/io.h>
-#include <dm/pinctrl.h>
-
-enum {
- /* GPIO0A_IOMUX */
- GPIO0A5_SEL_SHIFT = 10,
- GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT,
- GPIO0A5_I2C3_SCL = 2,
-
- GPIO0A6_SEL_SHIFT = 12,
- GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT,
- GPIO0A6_I2C3_SDA = 2,
-
- GPIO0A7_SEL_SHIFT = 14,
- GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT,
- GPIO0A7_EMMC_DATA0 = 2,
-
- /* GPIO0B_IOMUX*/
- GPIO0B0_SEL_SHIFT = 0,
- GPIO0B0_SEL_MASK = 3 << GPIO0B0_SEL_SHIFT,
- GPIO0B0_GAMC_CLKTXM0 = 1,
-
- GPIO0B4_SEL_SHIFT = 8,
- GPIO0B4_SEL_MASK = 3 << GPIO0B4_SEL_SHIFT,
- GPIO0B4_GAMC_TXENM0 = 1,
-
- /* GPIO0C_IOMUX*/
- GPIO0C0_SEL_SHIFT = 0,
- GPIO0C0_SEL_MASK = 3 << GPIO0C0_SEL_SHIFT,
- GPIO0C0_GAMC_TXD1M0 = 1,
-
- GPIO0C1_SEL_SHIFT = 2,
- GPIO0C1_SEL_MASK = 3 << GPIO0C1_SEL_SHIFT,
- GPIO0C1_GAMC_TXD0M0 = 1,
-
- GPIO0C6_SEL_SHIFT = 12,
- GPIO0C6_SEL_MASK = 3 << GPIO0C6_SEL_SHIFT,
- GPIO0C6_GAMC_TXD2M0 = 1,
-
- GPIO0C7_SEL_SHIFT = 14,
- GPIO0C7_SEL_MASK = 3 << GPIO0C7_SEL_SHIFT,
- GPIO0C7_GAMC_TXD3M0 = 1,
-
- /* GPIO0D_IOMUX*/
- GPIO0D0_SEL_SHIFT = 0,
- GPIO0D0_SEL_MASK = 3 << GPIO0D0_SEL_SHIFT,
- GPIO0D0_GMAC_CLKM0 = 1,
-
- GPIO0D6_SEL_SHIFT = 12,
- GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT,
- GPIO0D6_GPIO = 0,
- GPIO0D6_SDMMC0_PWRENM1 = 3,
-
- /* GPIO1A_IOMUX */
- GPIO1A0_SEL_SHIFT = 0,
- GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT,
- GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
-
- /* GPIO1B_IOMUX */
- GPIO1B0_SEL_SHIFT = 0,
- GPIO1B0_SEL_MASK = 3 << GPIO1B0_SEL_SHIFT,
- GPIO1B0_GMAC_TXD1M1 = 2,
-
- GPIO1B1_SEL_SHIFT = 2,
- GPIO1B1_SEL_MASK = 3 << GPIO1B1_SEL_SHIFT,
- GPIO1B1_GMAC_TXD0M1 = 2,
-
- GPIO1B2_SEL_SHIFT = 4,
- GPIO1B2_SEL_MASK = 3 << GPIO1B2_SEL_SHIFT,
- GPIO1B2_GMAC_RXD1M1 = 2,
-
- GPIO1B3_SEL_SHIFT = 6,
- GPIO1B3_SEL_MASK = 3 << GPIO1B3_SEL_SHIFT,
- GPIO1B3_GMAC_RXD0M1 = 2,
-
- GPIO1B4_SEL_SHIFT = 8,
- GPIO1B4_SEL_MASK = 3 << GPIO1B4_SEL_SHIFT,
- GPIO1B4_GMAC_TXCLKM1 = 2,
-
- GPIO1B5_SEL_SHIFT = 10,
- GPIO1B5_SEL_MASK = 3 << GPIO1B5_SEL_SHIFT,
- GPIO1B5_GMAC_RXCLKM1 = 2,
-
- GPIO1B6_SEL_SHIFT = 12,
- GPIO1B6_SEL_MASK = 3 << GPIO1B6_SEL_SHIFT,
- GPIO1B6_GMAC_RXD3M1 = 2,
-
- GPIO1B7_SEL_SHIFT = 14,
- GPIO1B7_SEL_MASK = 3 << GPIO1B7_SEL_SHIFT,
- GPIO1B7_GMAC_RXD2M1 = 2,
-
- /* GPIO1C_IOMUX */
- GPIO1C0_SEL_SHIFT = 0,
- GPIO1C0_SEL_MASK = 3 << GPIO1C0_SEL_SHIFT,
- GPIO1C0_GMAC_TXD3M1 = 2,
-
- GPIO1C1_SEL_SHIFT = 2,
- GPIO1C1_SEL_MASK = 3 << GPIO1C1_SEL_SHIFT,
- GPIO1C1_GMAC_TXD2M1 = 2,
-
- GPIO1C3_SEL_SHIFT = 6,
- GPIO1C3_SEL_MASK = 3 << GPIO1C3_SEL_SHIFT,
- GPIO1C3_GMAC_MDIOM1 = 2,
-
- GPIO1C5_SEL_SHIFT = 10,
- GPIO1C5_SEL_MASK = 3 << GPIO1C5_SEL_SHIFT,
- GPIO1C5_GMAC_CLKM1 = 2,
-
- GPIO1C6_SEL_SHIFT = 12,
- GPIO1C6_SEL_MASK = 3 << GPIO1C6_SEL_SHIFT,
- GPIO1C6_GMAC_RXDVM1 = 2,
-
- GPIO1C7_SEL_SHIFT = 14,
- GPIO1C7_SEL_MASK = 3 << GPIO1C7_SEL_SHIFT,
- GPIO1C7_GMAC_MDCM1 = 2,
-
- /* GPIO1D_IOMUX */
- GPIO1D1_SEL_SHIFT = 2,
- GPIO1D1_SEL_MASK = 3 << GPIO1D1_SEL_SHIFT,
- GPIO1D1_GMAC_TXENM1 = 2,
-
- /* GPIO2A_IOMUX */
- GPIO2A0_SEL_SHIFT = 0,
- GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
- GPIO2A0_UART2_TX_M1 = 1,
-
- GPIO2A1_SEL_SHIFT = 2,
- GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
- GPIO2A1_UART2_RX_M1 = 1,
-
- GPIO2A2_SEL_SHIFT = 4,
- GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT,
- GPIO2A2_PWM_IR = 1,
-
- GPIO2A4_SEL_SHIFT = 8,
- GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT,
- GPIO2A4_PWM_0 = 1,
- GPIO2A4_I2C1_SDA,
-
- GPIO2A5_SEL_SHIFT = 10,
- GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT,
- GPIO2A5_PWM_1 = 1,
- GPIO2A5_I2C1_SCL,
-
- GPIO2A6_SEL_SHIFT = 12,
- GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT,
- GPIO2A6_PWM_2 = 1,
-
- GPIO2A7_SEL_SHIFT = 14,
- GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT,
- GPIO2A7_GPIO = 0,
- GPIO2A7_SDMMC0_PWRENM0,
-
- /* GPIO2BL_IOMUX */
- GPIO2BL0_SEL_SHIFT = 0,
- GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT,
- GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15,
-
- GPIO2BL3_SEL_SHIFT = 6,
- GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT,
- GPIO2BL3_SPI_CSN0_M0 = 1,
-
- GPIO2BL4_SEL_SHIFT = 8,
- GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT,
- GPIO2BL4_SPI_CSN1_M0 = 1,
-
- GPIO2BL5_SEL_SHIFT = 10,
- GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT,
- GPIO2BL5_I2C2_SDA = 1,
-
- GPIO2BL6_SEL_SHIFT = 12,
- GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT,
- GPIO2BL6_I2C2_SCL = 1,
-
- /* GPIO2D_IOMUX */
- GPIO2D0_SEL_SHIFT = 0,
- GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT,
- GPIO2D0_I2C0_SCL = 1,
-
- GPIO2D1_SEL_SHIFT = 2,
- GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT,
- GPIO2D1_I2C0_SDA = 1,
-
- GPIO2D4_SEL_SHIFT = 8,
- GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT,
- GPIO2D4_EMMC_DATA1234 = 0xaa,
-
- /* GPIO3C_IOMUX */
- GPIO3C0_SEL_SHIFT = 0,
- GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT,
- GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
-
- /* COM_IOMUX */
- IOMUX_SEL_UART2_SHIFT = 0,
- IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
- IOMUX_SEL_UART2_M0 = 0,
- IOMUX_SEL_UART2_M1,
-
- IOMUX_SEL_GMAC_SHIFT = 2,
- IOMUX_SEL_GMAC_MASK = 1 << IOMUX_SEL_GMAC_SHIFT,
- IOMUX_SEL_GMAC_M0 = 0,
- IOMUX_SEL_GMAC_M1,
-
- IOMUX_SEL_SPI_SHIFT = 4,
- IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT,
- IOMUX_SEL_SPI_M0 = 0,
- IOMUX_SEL_SPI_M1,
- IOMUX_SEL_SPI_M2,
-
- IOMUX_SEL_SDMMC_SHIFT = 7,
- IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT,
- IOMUX_SEL_SDMMC_M0 = 0,
- IOMUX_SEL_SDMMC_M1,
-
- IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT = 10,
- IOMUX_SEL_GMACM1_OPTIMIZATION_MASK = 1 << IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT,
- IOMUX_SEL_GMACM1_OPTIMIZATION_BEFORE = 0,
- IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER,
-
- /* GRF_GPIO1B_E */
- GRF_GPIO1B0_E_SHIFT = 0,
- GRF_GPIO1B0_E_MASK = 3 << GRF_GPIO1B0_E_SHIFT,
- GRF_GPIO1B1_E_SHIFT = 2,
- GRF_GPIO1B1_E_MASK = 3 << GRF_GPIO1B1_E_SHIFT,
- GRF_GPIO1B2_E_SHIFT = 4,
- GRF_GPIO1B2_E_MASK = 3 << GRF_GPIO1B2_E_SHIFT,
- GRF_GPIO1B3_E_SHIFT = 6,
- GRF_GPIO1B3_E_MASK = 3 << GRF_GPIO1B3_E_SHIFT,
- GRF_GPIO1B4_E_SHIFT = 8,
- GRF_GPIO1B4_E_MASK = 3 << GRF_GPIO1B4_E_SHIFT,
- GRF_GPIO1B5_E_SHIFT = 10,
- GRF_GPIO1B5_E_MASK = 3 << GRF_GPIO1B5_E_SHIFT,
- GRF_GPIO1B6_E_SHIFT = 12,
- GRF_GPIO1B6_E_MASK = 3 << GRF_GPIO1B6_E_SHIFT,
- GRF_GPIO1B7_E_SHIFT = 14,
- GRF_GPIO1B7_E_MASK = 3 << GRF_GPIO1B7_E_SHIFT,
-
- /* GRF_GPIO1C_E */
- GRF_GPIO1C0_E_SHIFT = 0,
- GRF_GPIO1C0_E_MASK = 3 << GRF_GPIO1C0_E_SHIFT,
- GRF_GPIO1C1_E_SHIFT = 2,
- GRF_GPIO1C1_E_MASK = 3 << GRF_GPIO1C1_E_SHIFT,
- GRF_GPIO1C3_E_SHIFT = 6,
- GRF_GPIO1C3_E_MASK = 3 << GRF_GPIO1C3_E_SHIFT,
- GRF_GPIO1C5_E_SHIFT = 10,
- GRF_GPIO1C5_E_MASK = 3 << GRF_GPIO1C5_E_SHIFT,
- GRF_GPIO1C6_E_SHIFT = 12,
- GRF_GPIO1C6_E_MASK = 3 << GRF_GPIO1C6_E_SHIFT,
- GRF_GPIO1C7_E_SHIFT = 14,
- GRF_GPIO1C7_E_MASK = 3 << GRF_GPIO1C7_E_SHIFT,
-
- /* GRF_GPIO1D_E */
- GRF_GPIO1D1_E_SHIFT = 2,
- GRF_GPIO1D1_E_MASK = 3 << GRF_GPIO1D1_E_SHIFT,
-};
-
-/* GPIO Bias drive strength settings */
-enum GPIO_BIAS {
- GPIO_BIAS_2MA = 0,
- GPIO_BIAS_4MA,
- GPIO_BIAS_8MA,
- GPIO_BIAS_12MA,
-};
-
-struct rk3328_pinctrl_priv {
- struct rk3328_grf_regs *grf;
-};
-
-static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id)
-{
- switch (pwm_id) {
- case PERIPH_ID_PWM0:
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A4_SEL_MASK,
- GPIO2A4_PWM_0 << GPIO2A4_SEL_SHIFT);
- break;
- case PERIPH_ID_PWM1:
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A5_SEL_MASK,
- GPIO2A5_PWM_1 << GPIO2A5_SEL_SHIFT);
- break;
- case PERIPH_ID_PWM2:
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A6_SEL_MASK,
- GPIO2A6_PWM_2 << GPIO2A6_SEL_SHIFT);
- break;
- case PERIPH_ID_PWM3:
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A2_SEL_MASK,
- GPIO2A2_PWM_IR << GPIO2A2_SEL_SHIFT);
- break;
- default:
- debug("pwm id = %d iomux error!\n", pwm_id);
- break;
- }
-}
-
-static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id)
-{
- switch (i2c_id) {
- case PERIPH_ID_I2C0:
- rk_clrsetreg(&grf->gpio2d_iomux,
- GPIO2D0_SEL_MASK | GPIO2D1_SEL_MASK,
- GPIO2D0_I2C0_SCL << GPIO2D0_SEL_SHIFT |
- GPIO2D1_I2C0_SDA << GPIO2D1_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C1:
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A4_SEL_MASK | GPIO2A5_SEL_MASK,
- GPIO2A5_I2C1_SCL << GPIO2A5_SEL_SHIFT |
- GPIO2A4_I2C1_SDA << GPIO2A4_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C2:
- rk_clrsetreg(&grf->gpio2bl_iomux,
- GPIO2BL5_SEL_MASK | GPIO2BL6_SEL_MASK,
- GPIO2BL6_I2C2_SCL << GPIO2BL6_SEL_SHIFT |
- GPIO2BL5_I2C2_SDA << GPIO2BL5_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C3:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A5_SEL_MASK | GPIO0A6_SEL_MASK,
- GPIO0A5_I2C3_SCL << GPIO0A5_SEL_SHIFT |
- GPIO0A6_I2C3_SDA << GPIO0A6_SEL_SHIFT);
- break;
- default:
- debug("i2c id = %d iomux error!\n", i2c_id);
- break;
- }
-}
-
-static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id)
-{
- switch (lcd_id) {
- case PERIPH_ID_LCDC0:
- break;
- default:
- debug("lcdc id = %d iomux error!\n", lcd_id);
- break;
- }
-}
-
-static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf,
- enum periph_id spi_id, int cs)
-{
- u32 com_iomux = readl(&grf->com_iomux);
-
- if ((com_iomux & IOMUX_SEL_SPI_MASK) !=
- IOMUX_SEL_SPI_M0 << IOMUX_SEL_SPI_SHIFT) {
- debug("driver do not support iomux other than m0\n");
- goto err;
- }
-
- switch (spi_id) {
- case PERIPH_ID_SPI0:
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio2bl_iomux,
- GPIO2BL3_SEL_MASK,
- GPIO2BL3_SPI_CSN0_M0
- << GPIO2BL3_SEL_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio2bl_iomux,
- GPIO2BL4_SEL_MASK,
- GPIO2BL4_SPI_CSN1_M0
- << GPIO2BL4_SEL_SHIFT);
- break;
- default:
- goto err;
- }
- rk_clrsetreg(&grf->gpio2bl_iomux,
- GPIO2BL0_SEL_MASK,
- GPIO2BL0_SPI_CLK_TX_RX_M0 << GPIO2BL0_SEL_SHIFT);
- break;
- default:
- goto err;
- }
-
- return 0;
-err:
- debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
- return -ENOENT;
-}
-
-static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id)
-{
- u32 com_iomux = readl(&grf->com_iomux);
-
- switch (uart_id) {
- case PERIPH_ID_UART2:
- break;
- if (com_iomux & IOMUX_SEL_UART2_MASK)
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A0_SEL_MASK | GPIO2A1_SEL_MASK,
- GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT |
- GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
-
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART3:
- case PERIPH_ID_UART4:
- default:
- debug("uart id = %d iomux error!\n", uart_id);
- break;
- }
-}
-
-static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
- int mmc_id)
-{
- u32 com_iomux = readl(&grf->com_iomux);
-
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A7_SEL_MASK,
- GPIO0A7_EMMC_DATA0 << GPIO0A7_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio2d_iomux,
- GPIO2D4_SEL_MASK,
- GPIO2D4_EMMC_DATA1234 << GPIO2D4_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio3c_iomux,
- GPIO3C0_SEL_MASK,
- GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD
- << GPIO3C0_SEL_SHIFT);
- break;
- case PERIPH_ID_SDCARD:
- /* SDMMC_PWREN use GPIO and init as regulator-fiexed */
- if (com_iomux & IOMUX_SEL_SDMMC_MASK)
- rk_clrsetreg(&grf->gpio0d_iomux,
- GPIO0D6_SEL_MASK,
- GPIO0D6_GPIO << GPIO0D6_SEL_SHIFT);
- else
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A7_SEL_MASK,
- GPIO2A7_GPIO << GPIO2A7_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio1a_iomux,
- GPIO1A0_SEL_MASK,
- GPIO1A0_CARD_DATA_CLK_CMD_DETN
- << GPIO1A0_SEL_SHIFT);
- break;
- default:
- debug("mmc id = %d iomux error!\n", mmc_id);
- break;
- }
-}
-
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
-static void pinctrl_rk3328_gmac_config(struct rk3328_grf_regs *grf, int gmac_id)
-{
- switch (gmac_id) {
- case PERIPH_ID_GMAC:
- /* set rgmii m1 pins mux */
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B0_SEL_MASK |
- GPIO1B1_SEL_MASK |
- GPIO1B2_SEL_MASK |
- GPIO1B3_SEL_MASK |
- GPIO1B4_SEL_MASK |
- GPIO1B5_SEL_MASK |
- GPIO1B6_SEL_MASK |
- GPIO1B7_SEL_MASK,
- GPIO1B0_GMAC_TXD1M1 << GPIO1B0_SEL_SHIFT |
- GPIO1B1_GMAC_TXD0M1 << GPIO1B1_SEL_SHIFT |
- GPIO1B2_GMAC_RXD1M1 << GPIO1B2_SEL_SHIFT |
- GPIO1B3_GMAC_RXD0M1 << GPIO1B3_SEL_SHIFT |
- GPIO1B4_GMAC_TXCLKM1 << GPIO1B4_SEL_SHIFT |
- GPIO1B5_GMAC_RXCLKM1 << GPIO1B5_SEL_SHIFT |
- GPIO1B6_GMAC_RXD3M1 << GPIO1B6_SEL_SHIFT |
- GPIO1B7_GMAC_RXD2M1 << GPIO1B7_SEL_SHIFT);
-
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C0_SEL_MASK |
- GPIO1C1_SEL_MASK |
- GPIO1C3_SEL_MASK |
- GPIO1C5_SEL_MASK |
- GPIO1C6_SEL_MASK |
- GPIO1C7_SEL_MASK,
- GPIO1C0_GMAC_TXD3M1 << GPIO1C0_SEL_SHIFT |
- GPIO1C1_GMAC_TXD2M1 << GPIO1C1_SEL_SHIFT |
- GPIO1C3_GMAC_MDIOM1 << GPIO1C3_SEL_SHIFT |
- GPIO1C5_GMAC_CLKM1 << GPIO1C5_SEL_SHIFT |
- GPIO1C6_GMAC_RXDVM1 << GPIO1C6_SEL_SHIFT |
- GPIO1C7_GMAC_MDCM1 << GPIO1C7_SEL_SHIFT);
-
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D1_SEL_MASK,
- GPIO1D1_GMAC_TXENM1 << GPIO1D1_SEL_SHIFT);
-
- /* set rgmii m0 tx pins mux */
- rk_clrsetreg(&grf->gpio0b_iomux,
- GPIO0B0_SEL_MASK |
- GPIO0B4_SEL_MASK,
- GPIO0B0_GAMC_CLKTXM0 << GPIO0B0_SEL_SHIFT |
- GPIO0B4_GAMC_TXENM0 << GPIO0B4_SEL_SHIFT);
-
- rk_clrsetreg(&grf->gpio0c_iomux,
- GPIO0C0_SEL_MASK |
- GPIO0C1_SEL_MASK |
- GPIO0C6_SEL_MASK |
- GPIO0C7_SEL_MASK,
- GPIO0C0_GAMC_TXD1M0 << GPIO0C0_SEL_SHIFT |
- GPIO0C1_GAMC_TXD0M0 << GPIO0C1_SEL_SHIFT |
- GPIO0C6_GAMC_TXD2M0 << GPIO0C6_SEL_SHIFT |
- GPIO0C7_GAMC_TXD3M0 << GPIO0C7_SEL_SHIFT);
-
- rk_clrsetreg(&grf->gpio0d_iomux,
- GPIO0D0_SEL_MASK,
- GPIO0D0_GMAC_CLKM0 << GPIO0D0_SEL_SHIFT);
-
- /* set com mux */
- rk_clrsetreg(&grf->com_iomux,
- IOMUX_SEL_GMAC_MASK |
- IOMUX_SEL_GMACM1_OPTIMIZATION_MASK,
- IOMUX_SEL_GMAC_M1 << IOMUX_SEL_GMAC_SHIFT |
- IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER <<
- IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT);
-
- /*
- * set rgmii m1 tx pins to 12ma drive-strength,
- * and clean others to 2ma.
- */
- rk_clrsetreg(&grf->gpio1b_e,
- GRF_GPIO1B0_E_MASK |
- GRF_GPIO1B1_E_MASK |
- GRF_GPIO1B2_E_MASK |
- GRF_GPIO1B3_E_MASK |
- GRF_GPIO1B4_E_MASK |
- GRF_GPIO1B5_E_MASK |
- GRF_GPIO1B6_E_MASK |
- GRF_GPIO1B7_E_MASK,
- GPIO_BIAS_12MA << GRF_GPIO1B0_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO1B1_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1B2_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1B3_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO1B4_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1B5_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1B6_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1B7_E_SHIFT);
-
- rk_clrsetreg(&grf->gpio1c_e,
- GRF_GPIO1C0_E_MASK |
- GRF_GPIO1C1_E_MASK |
- GRF_GPIO1C3_E_MASK |
- GRF_GPIO1C5_E_MASK |
- GRF_GPIO1C6_E_MASK |
- GRF_GPIO1C7_E_MASK,
- GPIO_BIAS_12MA << GRF_GPIO1C0_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO1C1_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1C3_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1C5_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1C6_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1C7_E_SHIFT);
-
- rk_clrsetreg(&grf->gpio1d_e,
- GRF_GPIO1D1_E_MASK,
- GPIO_BIAS_12MA << GRF_GPIO1D1_E_SHIFT);
- break;
- default:
- debug("gmac id = %d iomux error!\n", gmac_id);
- break;
- }
-}
-#endif
-
-static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%x, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- pinctrl_rk3328_pwm_config(priv->grf, func);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- pinctrl_rk3328_i2c_config(priv->grf, func);
- break;
- case PERIPH_ID_SPI0:
- pinctrl_rk3328_spi_config(priv->grf, func, flags);
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- case PERIPH_ID_UART4:
- pinctrl_rk3328_uart_config(priv->grf, func);
- break;
- case PERIPH_ID_LCDC0:
- case PERIPH_ID_LCDC1:
- pinctrl_rk3328_lcdc_config(priv->grf, func);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- pinctrl_rk3328_sdmmc_config(priv->grf, func);
- break;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case PERIPH_ID_GMAC:
- pinctrl_rk3328_gmac_config(priv->grf, func);
- break;
-#endif
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk3328_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
- u32 cell[3];
- int ret;
-
- ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 49:
- return PERIPH_ID_SPI0;
- case 50:
- return PERIPH_ID_PWM0;
- case 36:
- return PERIPH_ID_I2C0;
- case 37: /* Note strange order */
- return PERIPH_ID_I2C1;
- case 38:
- return PERIPH_ID_I2C2;
- case 39:
- return PERIPH_ID_I2C3;
- case 12:
- return PERIPH_ID_SDCARD;
- case 14:
- return PERIPH_ID_EMMC;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case 24:
- return PERIPH_ID_GMAC;
-#endif
- }
-
- return -ENOENT;
-}
-
-static int rk3328_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk3328_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
-
- return rk3328_pinctrl_request(dev, func, 0);
-}
-
-static struct pinctrl_ops rk3328_pinctrl_ops = {
- .set_state_simple = rk3328_pinctrl_set_state_simple,
- .request = rk3328_pinctrl_request,
- .get_periph_id = rk3328_pinctrl_get_periph_id,
-};
-
-static int rk3328_pinctrl_probe(struct udevice *dev)
-{
- struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
- int ret = 0;
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- debug("%s: grf=%p\n", __func__, priv->grf);
-
- return ret;
-}
-
-static const struct udevice_id rk3328_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3328-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3328) = {
- .name = "rockchip_rk3328_pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = rk3328_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk3328_pinctrl_priv),
- .ops = &rk3328_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
- .probe = rk3328_pinctrl_probe,
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
- * Author: Andy Yan <andy.yan@rock-chips.com>
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/grf_rk3368.h>
-#include <asm/arch/periph.h>
-#include <dm/pinctrl.h>
-
-/* PMUGRF_GPIO0B_IOMUX */
-enum {
- GPIO0B5_SHIFT = 10,
- GPIO0B5_MASK = GENMASK(GPIO0B5_SHIFT + 1, GPIO0B5_SHIFT),
- GPIO0B5_GPIO = 0,
- GPIO0B5_SPI2_CSN0 = (2 << GPIO0B5_SHIFT),
-
- GPIO0B4_SHIFT = 8,
- GPIO0B4_MASK = GENMASK(GPIO0B4_SHIFT + 1, GPIO0B4_SHIFT),
- GPIO0B4_GPIO = 0,
- GPIO0B4_SPI2_CLK = (2 << GPIO0B4_SHIFT),
-
- GPIO0B3_SHIFT = 6,
- GPIO0B3_MASK = GENMASK(GPIO0B3_SHIFT + 1, GPIO0B3_SHIFT),
- GPIO0B3_GPIO = 0,
- GPIO0B3_SPI2_TXD = (2 << GPIO0B3_SHIFT),
-
- GPIO0B2_SHIFT = 4,
- GPIO0B2_MASK = GENMASK(GPIO0B2_SHIFT + 1, GPIO0B2_SHIFT),
- GPIO0B2_GPIO = 0,
- GPIO0B2_SPI2_RXD = (2 << GPIO0B2_SHIFT),
-};
-
-/*GRF_GPIO0C_IOMUX*/
-enum {
- GPIO0C7_SHIFT = 14,
- GPIO0C7_MASK = GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT),
- GPIO0C7_GPIO = 0,
- GPIO0C7_LCDC_D19 = (1 << GPIO0C7_SHIFT),
- GPIO0C7_TRACE_D9 = (2 << GPIO0C7_SHIFT),
- GPIO0C7_UART1_RTSN = (3 << GPIO0C7_SHIFT),
-
- GPIO0C6_SHIFT = 12,
- GPIO0C6_MASK = GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT),
- GPIO0C6_GPIO = 0,
- GPIO0C6_LCDC_D18 = (1 << GPIO0C6_SHIFT),
- GPIO0C6_TRACE_D8 = (2 << GPIO0C6_SHIFT),
- GPIO0C6_UART1_CTSN = (3 << GPIO0C6_SHIFT),
-
- GPIO0C5_SHIFT = 10,
- GPIO0C5_MASK = GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT),
- GPIO0C5_GPIO = 0,
- GPIO0C5_LCDC_D17 = (1 << GPIO0C5_SHIFT),
- GPIO0C5_TRACE_D7 = (2 << GPIO0C5_SHIFT),
- GPIO0C5_UART1_SOUT = (3 << GPIO0C5_SHIFT),
-
- GPIO0C4_SHIFT = 8,
- GPIO0C4_MASK = GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT),
- GPIO0C4_GPIO = 0,
- GPIO0C4_LCDC_D16 = (1 << GPIO0C4_SHIFT),
- GPIO0C4_TRACE_D6 = (2 << GPIO0C4_SHIFT),
- GPIO0C4_UART1_SIN = (3 << GPIO0C4_SHIFT),
-
- GPIO0C3_SHIFT = 6,
- GPIO0C3_MASK = GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT),
- GPIO0C3_GPIO = 0,
- GPIO0C3_LCDC_D15 = (1 << GPIO0C3_SHIFT),
- GPIO0C3_TRACE_D5 = (2 << GPIO0C3_SHIFT),
- GPIO0C3_MCU_JTAG_TDO = (3 << GPIO0C3_SHIFT),
-
- GPIO0C2_SHIFT = 4,
- GPIO0C2_MASK = GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT),
- GPIO0C2_GPIO = 0,
- GPIO0C2_LCDC_D14 = (1 << GPIO0C2_SHIFT),
- GPIO0C2_TRACE_D4 = (2 << GPIO0C2_SHIFT),
- GPIO0C2_MCU_JTAG_TDI = (3 << GPIO0C2_SHIFT),
-
- GPIO0C1_SHIFT = 2,
- GPIO0C1_MASK = GENMASK(GPIO0C1_SHIFT + 1, GPIO0C1_SHIFT),
- GPIO0C1_GPIO = 0,
- GPIO0C1_LCDC_D13 = (1 << GPIO0C1_SHIFT),
- GPIO0C1_TRACE_D3 = (2 << GPIO0C1_SHIFT),
- GPIO0C1_MCU_JTAG_TRTSN = (3 << GPIO0C1_SHIFT),
-
- GPIO0C0_SHIFT = 0,
- GPIO0C0_MASK = GENMASK(GPIO0C0_SHIFT + 1, GPIO0C0_SHIFT),
- GPIO0C0_GPIO = 0,
- GPIO0C0_LCDC_D12 = (1 << GPIO0C0_SHIFT),
- GPIO0C0_TRACE_D2 = (2 << GPIO0C0_SHIFT),
- GPIO0C0_MCU_JTAG_TDO = (3 << GPIO0C0_SHIFT),
-};
-
-/*GRF_GPIO0D_IOMUX*/
-enum {
- GPIO0D7_SHIFT = 14,
- GPIO0D7_MASK = GENMASK(GPIO0D7_SHIFT + 1, GPIO0D7_SHIFT),
- GPIO0D7_GPIO = 0,
- GPIO0D7_LCDC_DCLK = (1 << GPIO0D7_SHIFT),
- GPIO0D7_TRACE_CTL = (2 << GPIO0D7_SHIFT),
- GPIO0D7_PMU_DEBUG5 = (3 << GPIO0D7_SHIFT),
-
- GPIO0D6_SHIFT = 12,
- GPIO0D6_MASK = GENMASK(GPIO0D6_SHIFT + 1, GPIO0D6_SHIFT),
- GPIO0D6_GPIO = 0,
- GPIO0D6_LCDC_DEN = (1 << GPIO0D6_SHIFT),
- GPIO0D6_TRACE_CLK = (2 << GPIO0D6_SHIFT),
- GPIO0D6_PMU_DEBUG4 = (3 << GPIO0D6_SHIFT),
-
- GPIO0D5_SHIFT = 10,
- GPIO0D5_MASK = GENMASK(GPIO0D5_SHIFT + 1, GPIO0D5_SHIFT),
- GPIO0D5_GPIO = 0,
- GPIO0D5_LCDC_VSYNC = (1 << GPIO0D5_SHIFT),
- GPIO0D5_TRACE_D15 = (2 << GPIO0D5_SHIFT),
- GPIO0D5_PMU_DEBUG3 = (3 << GPIO0D5_SHIFT),
-
- GPIO0D4_SHIFT = 8,
- GPIO0D4_MASK = GENMASK(GPIO0D4_SHIFT + 1, GPIO0D4_SHIFT),
- GPIO0D4_GPIO = 0,
- GPIO0D4_LCDC_HSYNC = (1 << GPIO0D4_SHIFT),
- GPIO0D4_TRACE_D14 = (2 << GPIO0D4_SHIFT),
- GPIO0D4_PMU_DEBUG2 = (3 << GPIO0D4_SHIFT),
-
- GPIO0D3_SHIFT = 6,
- GPIO0D3_MASK = GENMASK(GPIO0D3_SHIFT + 1, GPIO0D3_SHIFT),
- GPIO0D3_GPIO = 0,
- GPIO0D3_LCDC_D23 = (1 << GPIO0D3_SHIFT),
- GPIO0D3_TRACE_D13 = (2 << GPIO0D3_SHIFT),
- GPIO0D3_UART4_SIN = (3 << GPIO0D3_SHIFT),
-
- GPIO0D2_SHIFT = 4,
- GPIO0D2_MASK = GENMASK(GPIO0D2_SHIFT + 1, GPIO0D2_SHIFT),
- GPIO0D2_GPIO = 0,
- GPIO0D2_LCDC_D22 = (1 << GPIO0D2_SHIFT),
- GPIO0D2_TRACE_D12 = (2 << GPIO0D2_SHIFT),
- GPIO0D2_UART4_SOUT = (3 << GPIO0D2_SHIFT),
-
- GPIO0D1_SHIFT = 2,
- GPIO0D1_MASK = GENMASK(GPIO0D1_SHIFT + 1, GPIO0D1_SHIFT),
- GPIO0D1_GPIO = 0,
- GPIO0D1_LCDC_D21 = (1 << GPIO0D1_SHIFT),
- GPIO0D1_TRACE_D11 = (2 << GPIO0D1_SHIFT),
- GPIO0D1_UART4_RTSN = (3 << GPIO0D1_SHIFT),
-
- GPIO0D0_SHIFT = 0,
- GPIO0D0_MASK = GENMASK(GPIO0D0_SHIFT + 1, GPIO0D0_SHIFT),
- GPIO0D0_GPIO = 0,
- GPIO0D0_LCDC_D20 = (1 << GPIO0D0_SHIFT),
- GPIO0D0_TRACE_D10 = (2 << GPIO0D0_SHIFT),
- GPIO0D0_UART4_CTSN = (3 << GPIO0D0_SHIFT),
-};
-
-/*GRF_GPIO2A_IOMUX*/
-enum {
- GPIO2A7_SHIFT = 14,
- GPIO2A7_MASK = GENMASK(GPIO2A7_SHIFT + 1, GPIO2A7_SHIFT),
- GPIO2A7_GPIO = 0,
- GPIO2A7_SDMMC0_D2 = (1 << GPIO2A7_SHIFT),
- GPIO2A7_JTAG_TCK = (2 << GPIO2A7_SHIFT),
-
- GPIO2A6_SHIFT = 12,
- GPIO2A6_MASK = GENMASK(GPIO2A6_SHIFT + 1, GPIO2A6_SHIFT),
- GPIO2A6_GPIO = 0,
- GPIO2A6_SDMMC0_D1 = (1 << GPIO2A6_SHIFT),
- GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
-
- GPIO2A5_SHIFT = 10,
- GPIO2A5_MASK = GENMASK(GPIO2A5_SHIFT + 1, GPIO2A5_SHIFT),
- GPIO2A5_GPIO = 0,
- GPIO2A5_SDMMC0_D0 = (1 << GPIO2A5_SHIFT),
- GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
-
- GPIO2A4_SHIFT = 8,
- GPIO2A4_MASK = GENMASK(GPIO2A4_SHIFT + 1, GPIO2A4_SHIFT),
- GPIO2A4_GPIO = 0,
- GPIO2A4_FLASH_DQS = (1 << GPIO2A4_SHIFT),
- GPIO2A4_EMMC_CLKOUT = (2 << GPIO2A4_SHIFT),
-
- GPIO2A3_SHIFT = 6,
- GPIO2A3_MASK = GENMASK(GPIO2A3_SHIFT + 1, GPIO2A3_SHIFT),
- GPIO2A3_GPIO = 0,
- GPIO2A3_FLASH_CSN3 = (1 << GPIO2A3_SHIFT),
- GPIO2A3_EMMC_RSTNOUT = (2 << GPIO2A3_SHIFT),
-
- GPIO2A2_SHIFT = 4,
- GPIO2A2_MASK = GENMASK(GPIO2A2_SHIFT + 1, GPIO2A2_SHIFT),
- GPIO2A2_GPIO = 0,
- GPIO2A2_FLASH_CSN2 = (1 << GPIO2A2_SHIFT),
-
- GPIO2A1_SHIFT = 2,
- GPIO2A1_MASK = GENMASK(GPIO2A1_SHIFT + 1, GPIO2A1_SHIFT),
- GPIO2A1_GPIO = 0,
- GPIO2A1_FLASH_CSN1 = (1 << GPIO2A1_SHIFT),
-
- GPIO2A0_SHIFT = 0,
- GPIO2A0_MASK = GENMASK(GPIO2A0_SHIFT + 1, GPIO2A0_SHIFT),
- GPIO2A0_GPIO = 0,
- GPIO2A0_FLASH_CSN0 = (1 << GPIO2A0_SHIFT),
-};
-
-/*GRF_GPIO2B_IOMUX*/
-enum {
- GPIO2B3_SHIFT = 6,
- GPIO2B3_MASK = GENMASK(GPIO2B3_SHIFT + 1, GPIO2B3_SHIFT),
- GPIO2B3_GPIO = 0,
- GPIO2B3_SDMMC0_DTECTN = (1 << GPIO2B3_SHIFT),
-
- GPIO2B2_SHIFT = 4,
- GPIO2B2_MASK = GENMASK(GPIO2B2_SHIFT + 1, GPIO2B2_SHIFT),
- GPIO2B2_GPIO = 0,
- GPIO2B2_SDMMC0_CMD = (1 << GPIO2B2_SHIFT),
-
- GPIO2B1_SHIFT = 2,
- GPIO2B1_MASK = GENMASK(GPIO2B1_SHIFT + 1, GPIO2B1_SHIFT),
- GPIO2B1_GPIO = 0,
- GPIO2B1_SDMMC0_CLKOUT = (1 << GPIO2B1_SHIFT),
-
- GPIO2B0_SHIFT = 0,
- GPIO2B0_MASK = GENMASK(GPIO2B0_SHIFT + 1, GPIO2B0_SHIFT),
- GPIO2B0_GPIO = 0,
- GPIO2B0_SDMMC0_D3 = (1 << GPIO2B0_SHIFT),
-};
-
-/*GRF_GPIO2D_IOMUX*/
-enum {
- GPIO2D7_SHIFT = 14,
- GPIO2D7_MASK = GENMASK(GPIO2D7_SHIFT + 1, GPIO2D7_SHIFT),
- GPIO2D7_GPIO = 0,
- GPIO2D7_SDIO0_D3 = (1 << GPIO2D7_SHIFT),
-
- GPIO2D6_SHIFT = 12,
- GPIO2D6_MASK = GENMASK(GPIO2D6_SHIFT + 1, GPIO2D6_SHIFT),
- GPIO2D6_GPIO = 0,
- GPIO2D6_SDIO0_D2 = (1 << GPIO2D6_SHIFT),
-
- GPIO2D5_SHIFT = 10,
- GPIO2D5_MASK = GENMASK(GPIO2D5_SHIFT + 1, GPIO2D5_SHIFT),
- GPIO2D5_GPIO = 0,
- GPIO2D5_SDIO0_D1 = (1 << GPIO2D5_SHIFT),
-
- GPIO2D4_SHIFT = 8,
- GPIO2D4_MASK = GENMASK(GPIO2D4_SHIFT + 1, GPIO2D4_SHIFT),
- GPIO2D4_GPIO = 0,
- GPIO2D4_SDIO0_D0 = (1 << GPIO2D4_SHIFT),
-
- GPIO2D3_SHIFT = 6,
- GPIO2D3_MASK = GENMASK(GPIO2D3_SHIFT + 1, GPIO2D3_SHIFT),
- GPIO2D3_GPIO = 0,
- GPIO2D3_UART0_RTS0 = (1 << GPIO2D3_SHIFT),
-
- GPIO2D2_SHIFT = 4,
- GPIO2D2_MASK = GENMASK(GPIO2D2_SHIFT + 1, GPIO2D2_SHIFT),
- GPIO2D2_GPIO = 0,
- GPIO2D2_UART0_CTS0 = (1 << GPIO2D2_SHIFT),
-
- GPIO2D1_SHIFT = 2,
- GPIO2D1_MASK = GENMASK(GPIO2D1_SHIFT + 1, GPIO2D1_SHIFT),
- GPIO2D1_GPIO = 0,
- GPIO2D1_UART0_SOUT = (1 << GPIO2D1_SHIFT),
-
- GPIO2D0_SHIFT = 0,
- GPIO2D0_MASK = GENMASK(GPIO2D0_SHIFT + 1, GPIO2D0_SHIFT),
- GPIO2D0_GPIO = 0,
- GPIO2D0_UART0_SIN = (1 << GPIO2D0_SHIFT),
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK = GENMASK(GPIO1B7_SHIFT + 1, GPIO1B7_SHIFT),
- GPIO1B7_GPIO = 0,
- GPIO1B7_SPI1_CSN0 = (2 << GPIO1B7_SHIFT),
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK = GENMASK(GPIO1B6_SHIFT + 1, GPIO1B6_SHIFT),
- GPIO1B6_GPIO = 0,
- GPIO1B6_SPI1_CLK = (2 << GPIO1B6_SHIFT),
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C7_SHIFT = 14,
- GPIO1C7_MASK = GENMASK(GPIO1C7_SHIFT + 1, GPIO1C7_SHIFT),
- GPIO1C7_GPIO = 0,
- GPIO1C7_EMMC_DATA5 = (2 << GPIO1C7_SHIFT),
- GPIO1C7_SPI0_TXD = (3 << GPIO1C7_SHIFT),
-
- GPIO1C6_SHIFT = 12,
- GPIO1C6_MASK = GENMASK(GPIO1C6_SHIFT + 1, GPIO1C6_SHIFT),
- GPIO1C6_GPIO = 0,
- GPIO1C6_EMMC_DATA4 = (2 << GPIO1C6_SHIFT),
- GPIO1C6_SPI0_RXD = (3 << GPIO1C6_SHIFT),
-
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK = GENMASK(GPIO1C5_SHIFT + 1, GPIO1C5_SHIFT),
- GPIO1C5_GPIO = 0,
- GPIO1C5_EMMC_DATA3 = (2 << GPIO1C5_SHIFT),
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK = GENMASK(GPIO1C4_SHIFT + 1, GPIO1C4_SHIFT),
- GPIO1C4_GPIO = 0,
- GPIO1C4_EMMC_DATA2 = (2 << GPIO1C4_SHIFT),
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK = GENMASK(GPIO1C3_SHIFT + 1, GPIO1C3_SHIFT),
- GPIO1C3_GPIO = 0,
- GPIO1C3_EMMC_DATA1 = (2 << GPIO1C3_SHIFT),
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK = GENMASK(GPIO1C2_SHIFT + 1, GPIO1C2_SHIFT),
- GPIO1C2_GPIO = 0,
- GPIO1C2_EMMC_DATA0 = (2 << GPIO1C2_SHIFT),
-
- GPIO1C1_SHIFT = 2,
- GPIO1C1_MASK = GENMASK(GPIO1C1_SHIFT + 1, GPIO1C1_SHIFT),
- GPIO1C1_GPIO = 0,
- GPIO1C1_SPI1_RXD = (2 << GPIO1C1_SHIFT),
-
- GPIO1C0_SHIFT = 0,
- GPIO1C0_MASK = GENMASK(GPIO1C0_SHIFT + 1, GPIO1C0_SHIFT),
- GPIO1C0_GPIO = 0,
- GPIO1C0_SPI1_TXD = (2 << GPIO1C0_SHIFT),
-};
-
-/* GRF_GPIO1D_IOMUX*/
-enum {
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK = GENMASK(GPIO1D5_SHIFT + 1, GPIO1D5_SHIFT),
- GPIO1D5_GPIO = 0,
- GPIO1D5_SPI0_CLK = (2 << GPIO1D5_SHIFT),
-
- GPIO1D3_SHIFT = 6,
- GPIO1D3_MASK = GENMASK(GPIO1D3_SHIFT + 1, GPIO1D3_SHIFT),
- GPIO1D3_GPIO = 0,
- GPIO1D3_EMMC_PWREN = (2 << GPIO1D3_SHIFT),
-
- GPIO1D2_SHIFT = 4,
- GPIO1D2_MASK = GENMASK(GPIO1D2_SHIFT + 1, GPIO1D2_SHIFT),
- GPIO1D2_GPIO = 0,
- GPIO1D2_EMMC_CMD = (2 << GPIO1D2_SHIFT),
-
- GPIO1D1_SHIFT = 2,
- GPIO1D1_MASK = GENMASK(GPIO1D1_SHIFT + 1, GPIO1D1_SHIFT),
- GPIO1D1_GPIO = 0,
- GPIO1D1_EMMC_DATA7 = (2 << GPIO1D1_SHIFT),
- GPIO1D1_SPI0_CSN1 = (3 << GPIO1D1_SHIFT),
-
- GPIO1D0_SHIFT = 0,
- GPIO1D0_MASK = GENMASK(GPIO1D0_SHIFT + 1, GPIO1D0_SHIFT),
- GPIO1D0_GPIO = 0,
- GPIO1D0_EMMC_DATA6 = (2 << GPIO1D0_SHIFT),
- GPIO1D0_SPI0_CSN0 = (3 << GPIO1D0_SHIFT),
-};
-
-
-/*GRF_GPIO3B_IOMUX*/
-enum {
- GPIO3B7_SHIFT = 14,
- GPIO3B7_MASK = GENMASK(GPIO3B7_SHIFT + 1, GPIO3B7_SHIFT),
- GPIO3B7_GPIO = 0,
- GPIO3B7_MAC_RXD0 = (1 << GPIO3B7_SHIFT),
-
- GPIO3B6_SHIFT = 12,
- GPIO3B6_MASK = GENMASK(GPIO3B6_SHIFT + 1, GPIO3B6_SHIFT),
- GPIO3B6_GPIO = 0,
- GPIO3B6_MAC_TXD3 = (1 << GPIO3B6_SHIFT),
-
- GPIO3B5_SHIFT = 10,
- GPIO3B5_MASK = GENMASK(GPIO3B5_SHIFT + 1, GPIO3B5_SHIFT),
- GPIO3B5_GPIO = 0,
- GPIO3B5_MAC_TXEN = (1 << GPIO3B5_SHIFT),
-
- GPIO3B4_SHIFT = 8,
- GPIO3B4_MASK = GENMASK(GPIO3B4_SHIFT + 1, GPIO3B4_SHIFT),
- GPIO3B4_GPIO = 0,
- GPIO3B4_MAC_COL = (1 << GPIO3B4_SHIFT),
-
- GPIO3B3_SHIFT = 6,
- GPIO3B3_MASK = GENMASK(GPIO3B3_SHIFT + 1, GPIO3B3_SHIFT),
- GPIO3B3_GPIO = 0,
- GPIO3B3_MAC_CRS = (1 << GPIO3B3_SHIFT),
-
- GPIO3B2_SHIFT = 4,
- GPIO3B2_MASK = GENMASK(GPIO3B2_SHIFT + 1, GPIO3B2_SHIFT),
- GPIO3B2_GPIO = 0,
- GPIO3B2_MAC_TXD2 = (1 << GPIO3B2_SHIFT),
-
- GPIO3B1_SHIFT = 2,
- GPIO3B1_MASK = GENMASK(GPIO3B1_SHIFT + 1, GPIO3B1_SHIFT),
- GPIO3B1_GPIO = 0,
- GPIO3B1_MAC_TXD1 = (1 << GPIO3B1_SHIFT),
-
- GPIO3B0_SHIFT = 0,
- GPIO3B0_MASK = GENMASK(GPIO3B0_SHIFT + 1, GPIO3B0_SHIFT),
- GPIO3B0_GPIO = 0,
- GPIO3B0_MAC_TXD0 = (1 << GPIO3B0_SHIFT),
- GPIO3B0_PWM0 = (2 << GPIO3B0_SHIFT),
-};
-
-/*GRF_GPIO3C_IOMUX*/
-enum {
- GPIO3C6_SHIFT = 12,
- GPIO3C6_MASK = GENMASK(GPIO3C6_SHIFT + 1, GPIO3C6_SHIFT),
- GPIO3C6_GPIO = 0,
- GPIO3C6_MAC_CLK = (1 << GPIO3C6_SHIFT),
-
- GPIO3C5_SHIFT = 10,
- GPIO3C5_MASK = GENMASK(GPIO3C5_SHIFT + 1, GPIO3C5_SHIFT),
- GPIO3C5_GPIO = 0,
- GPIO3C5_MAC_RXEN = (1 << GPIO3C5_SHIFT),
-
- GPIO3C4_SHIFT = 8,
- GPIO3C4_MASK = GENMASK(GPIO3C4_SHIFT + 1, GPIO3C4_SHIFT),
- GPIO3C4_GPIO = 0,
- GPIO3C4_MAC_RXDV = (1 << GPIO3C4_SHIFT),
-
- GPIO3C3_SHIFT = 6,
- GPIO3C3_MASK = GENMASK(GPIO3C3_SHIFT + 1, GPIO3C3_SHIFT),
- GPIO3C3_GPIO = 0,
- GPIO3C3_MAC_MDC = (1 << GPIO3C3_SHIFT),
-
- GPIO3C2_SHIFT = 4,
- GPIO3C2_MASK = GENMASK(GPIO3C2_SHIFT + 1, GPIO3C2_SHIFT),
- GPIO3C2_GPIO = 0,
- GPIO3C2_MAC_RXD3 = (1 << GPIO3C2_SHIFT),
-
- GPIO3C1_SHIFT = 2,
- GPIO3C1_MASK = GENMASK(GPIO3C1_SHIFT + 1, GPIO3C1_SHIFT),
- GPIO3C1_GPIO = 0,
- GPIO3C1_MAC_RXD2 = (1 << GPIO3C1_SHIFT),
-
- GPIO3C0_SHIFT = 0,
- GPIO3C0_MASK = GENMASK(GPIO3C0_SHIFT + 1, GPIO3C0_SHIFT),
- GPIO3C0_GPIO = 0,
- GPIO3C0_MAC_RXD1 = (1 << GPIO3C0_SHIFT),
-};
-
-/*GRF_GPIO3D_IOMUX*/
-enum {
- GPIO3D4_SHIFT = 8,
- GPIO3D4_MASK = GENMASK(GPIO3D4_SHIFT + 1, GPIO3D4_SHIFT),
- GPIO3D4_GPIO = 0,
- GPIO3D4_MAC_TXCLK = (1 << GPIO3D4_SHIFT),
- GPIO3D4_SPI1_CNS1 = (2 << GPIO3D4_SHIFT),
-
- GPIO3D1_SHIFT = 2,
- GPIO3D1_MASK = GENMASK(GPIO3D1_SHIFT + 1, GPIO3D1_SHIFT),
- GPIO3D1_GPIO = 0,
- GPIO3D1_MAC_RXCLK = (1 << GPIO3D1_SHIFT),
-
- GPIO3D0_SHIFT = 0,
- GPIO3D0_MASK = GENMASK(GPIO3D0_SHIFT + 1, GPIO3D0_SHIFT),
- GPIO3D0_GPIO = 0,
- GPIO3D0_MAC_MDIO = (1 << GPIO3D0_SHIFT),
-};
-
-struct rk3368_pinctrl_priv {
- struct rk3368_grf *grf;
- struct rk3368_pmu_grf *pmugrf;
-};
-
-static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
- int uart_id)
-{
- struct rk3368_grf *grf = priv->grf;
- struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
-
- switch (uart_id) {
- case PERIPH_ID_UART2:
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A6_MASK | GPIO2A5_MASK,
- GPIO2A6_UART2_SIN | GPIO2A5_UART2_SOUT);
- break;
- case PERIPH_ID_UART0:
- break;
- case PERIPH_ID_UART1:
- break;
- case PERIPH_ID_UART3:
- break;
- case PERIPH_ID_UART4:
- rk_clrsetreg(&pmugrf->gpio0d_iomux,
- GPIO0D0_MASK | GPIO0D1_MASK |
- GPIO0D2_MASK | GPIO0D3_MASK,
- GPIO0D0_GPIO | GPIO0D1_GPIO |
- GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
- break;
- default:
- debug("uart id = %d iomux error!\n", uart_id);
- break;
- }
-}
-
-static void pinctrl_rk3368_spi_config(struct rk3368_pinctrl_priv *priv,
- int spi_id)
-{
- struct rk3368_grf *grf = priv->grf;
- struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
-
- switch (spi_id) {
- case PERIPH_ID_SPI0:
- /*
- * eMMC can only be connected with 4 bits, when SPI0 is used.
- * This is all-or-nothing, so we assume that if someone asks us
- * to configure SPI0, that their eMMC interface is unused or
- * configured appropriately.
- */
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D0_MASK | GPIO1D1_MASK |
- GPIO1D5_MASK,
- GPIO1D0_SPI0_CSN0 | GPIO1D1_SPI0_CSN1 |
- GPIO1D5_SPI0_CLK);
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C6_MASK | GPIO1C7_MASK,
- GPIO1C6_SPI0_RXD | GPIO1C7_SPI0_TXD);
- break;
- case PERIPH_ID_SPI1:
- /*
- * We don't implement support for configuring SPI1_CSN#1, as it
- * conflicts with the GMAC (MAC TX clk-out).
- */
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B6_MASK | GPIO1B7_MASK,
- GPIO1B6_SPI1_CLK | GPIO1B7_SPI1_CSN0);
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C0_MASK | GPIO1C1_MASK,
- GPIO1C0_SPI1_TXD | GPIO1C1_SPI1_RXD);
- break;
- case PERIPH_ID_SPI2:
- rk_clrsetreg(&pmugrf->gpio0b_iomux,
- GPIO0B2_MASK | GPIO0B3_MASK |
- GPIO0B4_MASK | GPIO0B5_MASK,
- GPIO0B2_SPI2_RXD | GPIO0B3_SPI2_TXD |
- GPIO0B4_SPI2_CLK | GPIO0B5_SPI2_CSN0);
- break;
- default:
- debug("%s: spi id = %d iomux error!\n", __func__, spi_id);
- break;
- }
-}
-
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
-static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id)
-{
- rk_clrsetreg(&grf->gpio3b_iomux,
- GPIO3B0_MASK | GPIO3B1_MASK |
- GPIO3B2_MASK | GPIO3B5_MASK |
- GPIO3B6_MASK | GPIO3B7_MASK,
- GPIO3B0_MAC_TXD0 | GPIO3B1_MAC_TXD1 |
- GPIO3B2_MAC_TXD2 | GPIO3B5_MAC_TXEN |
- GPIO3B6_MAC_TXD3 | GPIO3B7_MAC_RXD0);
- rk_clrsetreg(&grf->gpio3c_iomux,
- GPIO3C0_MASK | GPIO3C1_MASK |
- GPIO3C2_MASK | GPIO3C3_MASK |
- GPIO3C4_MASK | GPIO3C5_MASK |
- GPIO3C6_MASK,
- GPIO3C0_MAC_RXD1 | GPIO3C1_MAC_RXD2 |
- GPIO3C2_MAC_RXD3 | GPIO3C3_MAC_MDC |
- GPIO3C4_MAC_RXDV | GPIO3C5_MAC_RXEN |
- GPIO3C6_MAC_CLK);
- rk_clrsetreg(&grf->gpio3d_iomux,
- GPIO3D0_MASK | GPIO3D1_MASK |
- GPIO3D4_MASK,
- GPIO3D0_MAC_MDIO | GPIO3D1_MAC_RXCLK |
- GPIO3D4_MAC_TXCLK);
-}
-#endif
-
-static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf *grf, int mmc_id)
-{
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- debug("mmc id = %d setting registers!\n", mmc_id);
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C2_MASK | GPIO1C3_MASK |
- GPIO1C4_MASK | GPIO1C5_MASK |
- GPIO1C6_MASK | GPIO1C7_MASK,
- GPIO1C2_EMMC_DATA0 |
- GPIO1C3_EMMC_DATA1 |
- GPIO1C4_EMMC_DATA2 |
- GPIO1C5_EMMC_DATA3 |
- GPIO1C6_EMMC_DATA4 |
- GPIO1C7_EMMC_DATA5);
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D0_MASK | GPIO1D1_MASK |
- GPIO1D2_MASK | GPIO1D3_MASK,
- GPIO1D0_EMMC_DATA6 |
- GPIO1D1_EMMC_DATA7 |
- GPIO1D2_EMMC_CMD |
- GPIO1D3_EMMC_PWREN);
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A3_MASK | GPIO2A4_MASK,
- GPIO2A3_EMMC_RSTNOUT |
- GPIO2A4_EMMC_CLKOUT);
- break;
- case PERIPH_ID_SDCARD:
- debug("mmc id = %d setting registers!\n", mmc_id);
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A5_MASK | GPIO2A7_MASK |
- GPIO2A7_MASK,
- GPIO2A5_SDMMC0_D0 | GPIO2A6_SDMMC0_D1 |
- GPIO2A7_SDMMC0_D2);
- rk_clrsetreg(&grf->gpio2b_iomux,
- GPIO2B0_MASK | GPIO2B1_MASK |
- GPIO2B2_MASK | GPIO2B3_MASK,
- GPIO2B0_SDMMC0_D3 | GPIO2B1_SDMMC0_CLKOUT |
- GPIO2B2_SDMMC0_CMD | GPIO2B3_SDMMC0_DTECTN);
- break;
- default:
- debug("mmc id = %d iomux error!\n", mmc_id);
- break;
- }
-}
-
-static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%d, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- case PERIPH_ID_UART4:
- pinctrl_rk3368_uart_config(priv, func);
- break;
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- case PERIPH_ID_SPI2:
- pinctrl_rk3368_spi_config(priv, func);
- break;
- case PERIPH_ID_EMMC:
- case PERIPH_ID_SDCARD:
- pinctrl_rk3368_sdmmc_config(priv->grf, func);
- break;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case PERIPH_ID_GMAC:
- pinctrl_rk3368_gmac_config(priv->grf, func);
- break;
-#endif
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
- u32 cell[3];
- int ret;
-
- ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 59:
- return PERIPH_ID_UART4;
- case 58:
- return PERIPH_ID_UART3;
- case 57:
- return PERIPH_ID_UART2;
- case 56:
- return PERIPH_ID_UART1;
- case 55:
- return PERIPH_ID_UART0;
- case 44:
- return PERIPH_ID_SPI0;
- case 45:
- return PERIPH_ID_SPI1;
- case 41:
- return PERIPH_ID_SPI2;
- case 35:
- return PERIPH_ID_EMMC;
- case 32:
- return PERIPH_ID_SDCARD;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case 27:
- return PERIPH_ID_GMAC;
-#endif
- }
-
- return -ENOENT;
-}
-
-static int rk3368_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk3368_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
-
- return rk3368_pinctrl_request(dev, func, 0);
-}
-
-static struct pinctrl_ops rk3368_pinctrl_ops = {
- .set_state_simple = rk3368_pinctrl_set_state_simple,
- .request = rk3368_pinctrl_request,
- .get_periph_id = rk3368_pinctrl_get_periph_id,
-};
-
-static int rk3368_pinctrl_probe(struct udevice *dev)
-{
- struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
- int ret = 0;
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
-
- debug("%s: grf=%p pmugrf:%p\n", __func__, priv->grf, priv->pmugrf);
-
- return ret;
-}
-
-static const struct udevice_id rk3368_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3368-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3368) = {
- .name = "rockchip_rk3368_pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = rk3368_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk3368_pinctrl_priv),
- .ops = &rk3368_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
- .probe = rk3368_pinctrl_probe,
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- * (C) 2018 Theobroma Systems Design und Consulting GmbH
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/grf_rk3399.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/clock.h>
-#include <dm/pinctrl.h>
-
-#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
-static const u32 RK_GRF_P_PULLUP = 1;
-static const u32 RK_GRF_P_PULLDOWN = 2;
-#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
-
-struct rk3399_pinctrl_priv {
- struct rk3399_grf_regs *grf;
- struct rk3399_pmugrf_regs *pmugrf;
- struct rockchip_pin_bank *banks;
-};
-
-#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
-/* Location of pinctrl/pinconf registers. */
-enum rk_grf_location {
- RK_GRF,
- RK_PMUGRF,
-};
-
-/**
- * @nr_pins: number of pins in this bank
- * @grf_location: location of pinctrl/pinconf registers
- * @bank_num: number of the bank, to account for holes
- * @iomux: array describing the 4 iomux sources of the bank
- */
-struct rockchip_pin_bank {
- u8 nr_pins;
- enum rk_grf_location grf_location;
- size_t iomux_offset;
- size_t pupd_offset;
-};
-
-#define PIN_BANK(pins, grf, iomux, pupd) \
- { \
- .nr_pins = pins, \
- .grf_location = grf, \
- .iomux_offset = iomux, \
- .pupd_offset = pupd, \
- }
-
-static struct rockchip_pin_bank rk3399_pin_banks[] = {
- PIN_BANK(16, RK_PMUGRF,
- offsetof(struct rk3399_pmugrf_regs, gpio0a_iomux),
- offsetof(struct rk3399_pmugrf_regs, gpio0_p)),
- PIN_BANK(32, RK_PMUGRF,
- offsetof(struct rk3399_pmugrf_regs, gpio1a_iomux),
- offsetof(struct rk3399_pmugrf_regs, gpio1_p)),
- PIN_BANK(32, RK_GRF,
- offsetof(struct rk3399_grf_regs, gpio2a_iomux),
- offsetof(struct rk3399_grf_regs, gpio2_p)),
- PIN_BANK(32, RK_GRF,
- offsetof(struct rk3399_grf_regs, gpio3a_iomux),
- offsetof(struct rk3399_grf_regs, gpio3_p)),
- PIN_BANK(32, RK_GRF,
- offsetof(struct rk3399_grf_regs, gpio4a_iomux),
- offsetof(struct rk3399_grf_regs, gpio4_p)),
-};
-
-static void rk_pinctrl_get_info(uintptr_t base, u32 index, uintptr_t *addr,
- u32 *shift, u32 *mask)
-{
- /*
- * In general we four subsequent 32-bit configuration registers
- * per bank (e.g. GPIO2A_P, GPIO2B_P, GPIO2C_P, GPIO2D_P).
- * The configuration for each pin has two bits.
- *
- * @base...contains the address to the first register.
- * @index...defines the pin within the bank (0..31).
- * @addr...will be the address of the actual register to use
- * @shift...will be the bit position in the configuration register
- * @mask...will be the (unshifted) mask
- */
-
- const u32 pins_per_register = 8;
- const u32 config_bits_per_pin = 2;
-
- /* Get the address of the configuration register. */
- *addr = base + (index / pins_per_register) * sizeof(u32);
-
- /* Get the bit offset within the configuration register. */
- *shift = (index & (pins_per_register - 1)) * config_bits_per_pin;
-
- /* Get the (unshifted) mask for the configuration pins. */
- *mask = ((1 << config_bits_per_pin) - 1);
-
- pr_debug("%s: addr=0x%lx, mask=0x%x, shift=0x%x\n",
- __func__, *addr, *mask, *shift);
-}
-
-static void rk3399_pinctrl_set_pin_iomux(uintptr_t grf_addr,
- struct rockchip_pin_bank *bank,
- u32 index, u32 muxval)
-{
- uintptr_t iomux_base, addr;
- u32 shift, mask;
-
- iomux_base = grf_addr + bank->iomux_offset;
- rk_pinctrl_get_info(iomux_base, index, &addr, &shift, &mask);
-
- /* Set pinmux register */
- rk_clrsetreg(addr, mask << shift, muxval << shift);
-}
-
-static void rk3399_pinctrl_set_pin_pupd(uintptr_t grf_addr,
- struct rockchip_pin_bank *bank,
- u32 index, int pinconfig)
-{
- uintptr_t pupd_base, addr;
- u32 shift, mask, pupdval;
-
- /* Fast path in case there's nothing to do. */
- if (!pinconfig)
- return;
-
- if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_UP))
- pupdval = RK_GRF_P_PULLUP;
- else if (pinconfig & (1 << PIN_CONFIG_BIAS_PULL_DOWN)) {
- pupdval = RK_GRF_P_PULLDOWN;
- } else {
- /* Flag not supported. */
- pr_warn("%s: Unsupported pinconfig flag: 0x%x\n", __func__,
- pinconfig);
- return;
- }
-
- pupd_base = grf_addr + (uintptr_t)bank->pupd_offset;
- rk_pinctrl_get_info(pupd_base, index, &addr, &shift, &mask);
-
- /* Set pull-up/pull-down regisrer */
- rk_clrsetreg(addr, mask << shift, pupdval << shift);
-}
-
-static int rk3399_pinctrl_set_pin(struct udevice *dev, u32 banknum, u32 index,
- u32 muxval, int pinconfig)
-{
- struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
- struct rockchip_pin_bank *bank = &priv->banks[banknum];
- uintptr_t grf_addr;
-
- pr_debug("%s: 0x%x 0x%x 0x%x 0x%x\n", __func__, banknum, index, muxval,
- pinconfig);
-
- if (bank->grf_location == RK_GRF)
- grf_addr = (uintptr_t)priv->grf;
- else if (bank->grf_location == RK_PMUGRF)
- grf_addr = (uintptr_t)priv->pmugrf;
- else
- return -EINVAL;
-
- rk3399_pinctrl_set_pin_iomux(grf_addr, bank, index, muxval);
-
- rk3399_pinctrl_set_pin_pupd(grf_addr, bank, index, pinconfig);
- return 0;
-}
-
-static int rk3399_pinctrl_set_state(struct udevice *dev, struct udevice *config)
-{
- /*
- * The order of the fields in this struct must match the order of
- * the fields in the "rockchip,pins" property.
- */
- struct rk_pin {
- u32 banknum;
- u32 index;
- u32 muxval;
- u32 phandle;
- } __packed;
-
- u32 *fields = NULL;
- const int fields_per_pin = 4;
- int num_fields, num_pins;
- int ret;
- int size;
- int i;
- struct rk_pin *pin;
-
- pr_debug("%s: %s\n", __func__, config->name);
-
- size = dev_read_size(config, "rockchip,pins");
- if (size < 0)
- return -EINVAL;
-
- num_fields = size / sizeof(u32);
- num_pins = num_fields / fields_per_pin;
-
- if (num_fields * sizeof(u32) != size ||
- num_pins * fields_per_pin != num_fields) {
- pr_warn("Invalid number of rockchip,pins fields.\n");
- return -EINVAL;
- }
-
- fields = calloc(num_fields, sizeof(u32));
- if (!fields)
- return -ENOMEM;
-
- ret = dev_read_u32_array(config, "rockchip,pins", fields, num_fields);
- if (ret) {
- pr_warn("%s: Failed to read rockchip,pins fields.\n",
- config->name);
- goto end;
- }
-
- pin = (struct rk_pin *)fields;
- for (i = 0; i < num_pins; i++, pin++) {
- struct udevice *dev_pinconfig;
- int pinconfig;
-
- ret = uclass_get_device_by_phandle_id(UCLASS_PINCONFIG,
- pin->phandle,
- &dev_pinconfig);
- if (ret) {
- pr_debug("Could not get pinconfig device\n");
- goto end;
- }
-
- pinconfig = pinctrl_decode_pin_config_dm(dev_pinconfig);
- if (pinconfig < 0) {
- pr_warn("Could not parse pinconfig\n");
- goto end;
- }
-
- ret = rk3399_pinctrl_set_pin(dev, pin->banknum, pin->index,
- pin->muxval, pinconfig);
- if (ret) {
- pr_warn("Could not set pinctrl settings\n");
- goto end;
- }
- }
-
-end:
- free(fields);
- return ret;
-}
-
-#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
-
-static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
- struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
-{
- switch (pwm_id) {
- case PERIPH_ID_PWM0:
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C2_SEL_MASK,
- GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT);
- break;
- case PERIPH_ID_PWM1:
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C6_SEL_MASK,
- GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT);
- break;
- case PERIPH_ID_PWM2:
- rk_clrsetreg(&pmugrf->gpio1c_iomux,
- PMUGRF_GPIO1C3_SEL_MASK,
- PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT);
- break;
- case PERIPH_ID_PWM3:
- if (readl(&pmugrf->soc_con0) & (1 << 5))
- rk_clrsetreg(&pmugrf->gpio1b_iomux,
- PMUGRF_GPIO1B6_SEL_MASK,
- PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT);
- else
- rk_clrsetreg(&pmugrf->gpio0a_iomux,
- PMUGRF_GPIO0A6_SEL_MASK,
- PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT);
- break;
- default:
- debug("pwm id = %d iomux error!\n", pwm_id);
- break;
- }
-}
-
-static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
- struct rk3399_pmugrf_regs *pmugrf,
- int i2c_id)
-{
- switch (i2c_id) {
- case PERIPH_ID_I2C0:
- rk_clrsetreg(&pmugrf->gpio1b_iomux,
- PMUGRF_GPIO1B7_SEL_MASK,
- PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT);
- rk_clrsetreg(&pmugrf->gpio1c_iomux,
- PMUGRF_GPIO1C0_SEL_MASK,
- PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
- break;
-
- case PERIPH_ID_I2C1:
- rk_clrsetreg(&grf->gpio4a_iomux,
- GRF_GPIO4A1_SEL_MASK,
- GRF_I2C1_SDA << GRF_GPIO4A1_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio4a_iomux,
- GRF_GPIO4A2_SEL_MASK,
- GRF_I2C1_SCL << GRF_GPIO4A2_SEL_SHIFT);
- break;
-
- case PERIPH_ID_I2C2:
- rk_clrsetreg(&grf->gpio2a_iomux,
- GRF_GPIO2A0_SEL_MASK,
- GRF_I2C2_SDA << GRF_GPIO2A0_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio2a_iomux,
- GRF_GPIO2A1_SEL_MASK,
- GRF_I2C2_SCL << GRF_GPIO2A1_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C3:
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C0_SEL_MASK,
- GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C1_SEL_MASK,
- GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT);
- break;
-
- case PERIPH_ID_I2C4:
- rk_clrsetreg(&pmugrf->gpio1b_iomux,
- PMUGRF_GPIO1B3_SEL_MASK,
- PMUGRF_I2C4_SDA << PMUGRF_GPIO1B3_SEL_SHIFT);
- rk_clrsetreg(&pmugrf->gpio1b_iomux,
- PMUGRF_GPIO1B4_SEL_MASK,
- PMUGRF_I2C4_SCL << PMUGRF_GPIO1B4_SEL_SHIFT);
- break;
-
- case PERIPH_ID_I2C7:
- rk_clrsetreg(&grf->gpio2a_iomux,
- GRF_GPIO2A7_SEL_MASK,
- GRF_I2C7_SDA << GRF_GPIO2A7_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio2b_iomux,
- GRF_GPIO2B0_SEL_MASK,
- GRF_I2C7_SCL << GRF_GPIO2B0_SEL_SHIFT);
- break;
-
- case PERIPH_ID_I2C6:
- rk_clrsetreg(&grf->gpio2b_iomux,
- GRF_GPIO2B1_SEL_MASK,
- GRF_I2C6_SDA << GRF_GPIO2B1_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio2b_iomux,
- GRF_GPIO2B2_SEL_MASK,
- GRF_I2C6_SDA << GRF_GPIO2B2_SEL_SHIFT);
- break;
-
- case PERIPH_ID_I2C8:
- rk_clrsetreg(&pmugrf->gpio1c_iomux,
- PMUGRF_GPIO1C4_SEL_MASK,
- PMUGRF_I2C8PMU_SDA << PMUGRF_GPIO1C4_SEL_SHIFT);
- rk_clrsetreg(&pmugrf->gpio1c_iomux,
- PMUGRF_GPIO1C5_SEL_MASK,
- PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT);
- break;
-
- case PERIPH_ID_I2C5:
- default:
- debug("i2c id = %d iomux error!\n", i2c_id);
- break;
- }
-}
-
-static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id)
-{
- switch (lcd_id) {
- case PERIPH_ID_LCDC0:
- break;
- default:
- debug("lcdc id = %d iomux error!\n", lcd_id);
- break;
- }
-}
-
-static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
- struct rk3399_pmugrf_regs *pmugrf,
- enum periph_id spi_id, int cs)
-{
- switch (spi_id) {
- case PERIPH_ID_SPI0:
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio3a_iomux,
- GRF_GPIO3A7_SEL_MASK,
- GRF_SPI0NORCODEC_CSN0
- << GRF_GPIO3A7_SEL_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio3b_iomux,
- GRF_GPIO3B0_SEL_MASK,
- GRF_SPI0NORCODEC_CSN1
- << GRF_GPIO3B0_SEL_SHIFT);
- break;
- default:
- goto err;
- }
- rk_clrsetreg(&grf->gpio3a_iomux,
- GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT
- | GRF_GPIO3A6_SEL_SHIFT,
- GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT
- | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT
- | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT);
- break;
- case PERIPH_ID_SPI1:
- if (cs != 0)
- goto err;
- rk_clrsetreg(&pmugrf->gpio1a_iomux,
- PMUGRF_GPIO1A7_SEL_MASK,
- PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT);
- rk_clrsetreg(&pmugrf->gpio1b_iomux,
- PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK
- | PMUGRF_GPIO1B2_SEL_MASK,
- PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT
- | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT
- | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT);
- break;
- case PERIPH_ID_SPI2:
- if (cs != 0)
- goto err;
- rk_clrsetreg(&grf->gpio2b_iomux,
- GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK
- | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK,
- GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT
- | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT
- | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
- | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
- break;
- case PERIPH_ID_SPI5:
- if (cs != 0)
- goto err;
- rk_clrsetreg(&grf->gpio2c_iomux,
- GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK
- | GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK,
- GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT
- | GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT
- | GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT
- | GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT);
- break;
- default:
- printf("%s: spi_id %d is not supported.\n", __func__, spi_id);
- goto err;
- }
-
- return 0;
-err:
- debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
- return -ENOENT;
-}
-
-static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf,
- struct rk3399_pmugrf_regs *pmugrf,
- int uart_id)
-{
- switch (uart_id) {
- case PERIPH_ID_UART2:
- /* Using channel-C by default */
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C3_SEL_MASK,
- GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C4_SEL_MASK,
- GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART3:
- case PERIPH_ID_UART4:
- default:
- debug("uart id = %d iomux error!\n", uart_id);
- break;
- }
-}
-
-static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
-{
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- break;
- case PERIPH_ID_SDCARD:
- rk_clrsetreg(&grf->gpio4b_iomux,
- GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK
- | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK
- | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK,
- GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT
- | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT
- | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT
- | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT
- | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT
- | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT);
- break;
- default:
- debug("mmc id = %d iomux error!\n", mmc_id);
- break;
- }
-}
-
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
-static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id)
-{
- rk_clrsetreg(&grf->gpio3a_iomux,
- GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK |
- GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK |
- GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK |
- GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK,
- GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT |
- GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT |
- GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT |
- GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT |
- GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT |
- GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT |
- GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT |
- GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio3b_iomux,
- GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK |
- GRF_GPIO3B3_SEL_MASK |
- GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK |
- GRF_GPIO3B6_SEL_MASK,
- GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT |
- GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT |
- GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT |
- GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT |
- GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT |
- GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio3c_iomux,
- GRF_GPIO3C1_SEL_MASK,
- GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT);
-
- /* Set drive strength for GMAC tx io, value 3 means 13mA */
- rk_clrsetreg(&grf->gpio3_e[0],
- GRF_GPIO3A0_E_MASK | GRF_GPIO3A1_E_MASK |
- GRF_GPIO3A4_E_MASK | GRF_GPIO3A5_E0_MASK,
- 3 << GRF_GPIO3A0_E_SHIFT |
- 3 << GRF_GPIO3A1_E_SHIFT |
- 3 << GRF_GPIO3A4_E_SHIFT |
- 1 << GRF_GPIO3A5_E0_SHIFT);
- rk_clrsetreg(&grf->gpio3_e[1],
- GRF_GPIO3A5_E12_MASK,
- 1 << GRF_GPIO3A5_E12_SHIFT);
- rk_clrsetreg(&grf->gpio3_e[2],
- GRF_GPIO3B4_E_MASK,
- 3 << GRF_GPIO3B4_E_SHIFT);
- rk_clrsetreg(&grf->gpio3_e[4],
- GRF_GPIO3C1_E_MASK,
- 3 << GRF_GPIO3C1_E_SHIFT);
-}
-#endif
-
-#if !defined(CONFIG_SPL_BUILD)
-static void pinctrl_rk3399_hdmi_config(struct rk3399_grf_regs *grf, int hdmi_id)
-{
- switch (hdmi_id) {
- case PERIPH_ID_HDMI:
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C0_SEL_MASK | GRF_GPIO4C1_SEL_MASK,
- (GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT) |
- (GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT));
- break;
- default:
- debug("%s: hdmi_id = %d unsupported\n", __func__, hdmi_id);
- break;
- }
-}
-#endif
-
-static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%x, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- case PERIPH_ID_PWM4:
- pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
- case PERIPH_ID_I2C8:
- pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func);
- break;
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- case PERIPH_ID_SPI2:
- case PERIPH_ID_SPI3:
- case PERIPH_ID_SPI4:
- case PERIPH_ID_SPI5:
- pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- case PERIPH_ID_UART4:
- pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func);
- break;
- case PERIPH_ID_LCDC0:
- case PERIPH_ID_LCDC1:
- pinctrl_rk3399_lcdc_config(priv->grf, func);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- pinctrl_rk3399_sdmmc_config(priv->grf, func);
- break;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case PERIPH_ID_GMAC:
- pinctrl_rk3399_gmac_config(priv->grf, func);
- break;
-#endif
-#if !defined(CONFIG_SPL_BUILD)
- case PERIPH_ID_HDMI:
- pinctrl_rk3399_hdmi_config(priv->grf, func);
- break;
-#endif
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- u32 cell[3];
- int ret;
-
- ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 68:
- return PERIPH_ID_SPI0;
- case 53:
- return PERIPH_ID_SPI1;
- case 52:
- return PERIPH_ID_SPI2;
- case 132:
- return PERIPH_ID_SPI5;
- case 57:
- return PERIPH_ID_I2C0;
- case 59: /* Note strange order */
- return PERIPH_ID_I2C1;
- case 35:
- return PERIPH_ID_I2C2;
- case 34:
- return PERIPH_ID_I2C3;
- case 56:
- return PERIPH_ID_I2C4;
- case 38:
- return PERIPH_ID_I2C5;
- case 37:
- return PERIPH_ID_I2C6;
- case 36:
- return PERIPH_ID_I2C7;
- case 58:
- return PERIPH_ID_I2C8;
- case 65:
- return PERIPH_ID_SDMMC1;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case 12:
- return PERIPH_ID_GMAC;
-#endif
-#if !defined(CONFIG_SPL_BUILD)
- case 23:
- return PERIPH_ID_HDMI;
-#endif
- }
-#endif
- return -ENOENT;
-}
-
-static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk3399_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
-
- return rk3399_pinctrl_request(dev, func, 0);
-}
-
-static struct pinctrl_ops rk3399_pinctrl_ops = {
-#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
- .set_state = rk3399_pinctrl_set_state,
-#endif
- .set_state_simple = rk3399_pinctrl_set_state_simple,
- .request = rk3399_pinctrl_request,
- .get_periph_id = rk3399_pinctrl_get_periph_id,
-};
-
-static int rk3399_pinctrl_probe(struct udevice *dev)
-{
- struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
- int ret = 0;
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
- debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);
-#if CONFIG_IS_ENABLED(PINCTRL_ROCKCHIP_RK3399_FULL)
- priv->banks = rk3399_pin_banks;
-#endif /* PINCTRL_ROCKCHIP_RK3399_FULL */
-
- return ret;
-}
-
-static const struct udevice_id rk3399_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3399-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3399) = {
- .name = "rockchip_rk3399_pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = rk3399_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv),
- .ops = &rk3399_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- .bind = dm_scan_fdt_dev,
-#endif
- .probe = rk3399_pinctrl_probe,
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- * Author: Andy Yan <andy.yan@rock-chips.com>
- */
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rv1108.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <dm/pinctrl.h>
-
-struct rv1108_pinctrl_priv {
- struct rv1108_grf *grf;
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
- GPIO1B7_GPIO = 0,
- GPIO1B7_LCDC_D12,
- GPIO1B7_I2S_SDIO2_M0,
- GPIO1B7_GMAC_RXDV,
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
- GPIO1B6_GPIO = 0,
- GPIO1B6_LCDC_D13,
- GPIO1B6_I2S_LRCLKTX_M0,
- GPIO1B6_GMAC_RXD1,
-
- GPIO1B5_SHIFT = 10,
- GPIO1B5_MASK = 3 << GPIO1B5_SHIFT,
- GPIO1B5_GPIO = 0,
- GPIO1B5_LCDC_D14,
- GPIO1B5_I2S_SDIO1_M0,
- GPIO1B5_GMAC_RXD0,
-
- GPIO1B4_SHIFT = 8,
- GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
- GPIO1B4_GPIO = 0,
- GPIO1B4_LCDC_D15,
- GPIO1B4_I2S_MCLK_M0,
- GPIO1B4_GMAC_TXEN,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
- GPIO1B3_GPIO = 0,
- GPIO1B3_LCDC_D16,
- GPIO1B3_I2S_SCLK_M0,
- GPIO1B3_GMAC_TXD1,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO = 0,
- GPIO1B2_LCDC_D17,
- GPIO1B2_I2S_SDIO_M0,
- GPIO1B2_GMAC_TXD0,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO = 0,
- GPIO1B1_LCDC_D9,
- GPIO1B1_PWM7,
-
- GPIO1B0_SHIFT = 0,
- GPIO1B0_MASK = 3,
- GPIO1B0_GPIO = 0,
- GPIO1B0_LCDC_D8,
- GPIO1B0_PWM6,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C7_SHIFT = 14,
- GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
- GPIO1C7_GPIO = 0,
- GPIO1C7_CIF_D5,
- GPIO1C7_I2S_SDIO2_M1,
-
- GPIO1C6_SHIFT = 12,
- GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
- GPIO1C6_GPIO = 0,
- GPIO1C6_CIF_D4,
- GPIO1C6_I2S_LRCLKTX_M1,
-
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
- GPIO1C5_GPIO = 0,
- GPIO1C5_LCDC_CLK,
- GPIO1C5_GMAC_CLK,
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
- GPIO1C4_GPIO = 0,
- GPIO1C4_LCDC_HSYNC,
- GPIO1C4_GMAC_MDC,
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
- GPIO1C3_GPIO = 0,
- GPIO1C3_LCDC_VSYNC,
- GPIO1C3_GMAC_MDIO,
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
- GPIO1C2_GPIO = 0,
- GPIO1C2_LCDC_EN,
- GPIO1C2_I2S_SDIO3_M0,
- GPIO1C2_GMAC_RXER,
-
- GPIO1C1_SHIFT = 2,
- GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
- GPIO1C1_GPIO = 0,
- GPIO1C1_LCDC_D10,
- GPIO1C1_I2S_SDI_M0,
- GPIO1C1_PWM4,
-
- GPIO1C0_SHIFT = 0,
- GPIO1C0_MASK = 3,
- GPIO1C0_GPIO = 0,
- GPIO1C0_LCDC_D11,
- GPIO1C0_I2S_LRCLKRX_M0,
-};
-
-/* GRF_GPIO1D_OIMUX */
-enum {
- GPIO1D7_SHIFT = 14,
- GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
- GPIO1D7_GPIO = 0,
- GPIO1D7_HDMI_CEC,
- GPIO1D7_DSP_RTCK,
-
- GPIO1D6_SHIFT = 12,
- GPIO1D6_MASK = 1 << GPIO1D6_SHIFT,
- GPIO1D6_GPIO = 0,
- GPIO1D6_HDMI_HPD_M0,
-
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
- GPIO1D5_GPIO = 0,
- GPIO1D5_UART2_RTSN,
- GPIO1D5_HDMI_SDA_M0,
-
- GPIO1D4_SHIFT = 8,
- GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
- GPIO1D4_GPIO = 0,
- GPIO1D4_UART2_CTSN,
- GPIO1D4_HDMI_SCL_M0,
-
- GPIO1D3_SHIFT = 6,
- GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
- GPIO1D3_GPIO = 0,
- GPIO1D3_UART0_SOUT,
- GPIO1D3_SPI_TXD_M0,
-
- GPIO1D2_SHIFT = 4,
- GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
- GPIO1D2_GPIO = 0,
- GPIO1D2_UART0_SIN,
- GPIO1D2_SPI_RXD_M0,
- GPIO1D2_DSP_TDI,
-
- GPIO1D1_SHIFT = 2,
- GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
- GPIO1D1_GPIO = 0,
- GPIO1D1_UART0_RTSN,
- GPIO1D1_SPI_CSN0_M0,
- GPIO1D1_DSP_TMS,
-
- GPIO1D0_SHIFT = 0,
- GPIO1D0_MASK = 3,
- GPIO1D0_GPIO = 0,
- GPIO1D0_UART0_CTSN,
- GPIO1D0_SPI_CLK_M0,
- GPIO1D0_DSP_TCK,
-};
-
-/* GRF_GPIO2A_IOMUX */
-enum {
- GPIO2A7_SHIFT = 14,
- GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
- GPIO2A7_GPIO = 0,
- GPIO2A7_FLASH_D7,
- GPIO2A7_EMMC_D7,
-
- GPIO2A6_SHIFT = 12,
- GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
- GPIO2A6_GPIO = 0,
- GPIO2A6_FLASH_D6,
- GPIO2A6_EMMC_D6,
-
- GPIO2A5_SHIFT = 10,
- GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
- GPIO2A5_GPIO = 0,
- GPIO2A5_FLASH_D5,
- GPIO2A5_EMMC_D5,
-
- GPIO2A4_SHIFT = 8,
- GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
- GPIO2A4_GPIO = 0,
- GPIO2A4_FLASH_D4,
- GPIO2A4_EMMC_D4,
-
- GPIO2A3_SHIFT = 6,
- GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
- GPIO2A3_GPIO = 0,
- GPIO2A3_FLASH_D3,
- GPIO2A3_EMMC_D3,
- GPIO2A3_SFC_HOLD_IO3,
-
- GPIO2A2_SHIFT = 4,
- GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
- GPIO2A2_GPIO = 0,
- GPIO2A2_FLASH_D2,
- GPIO2A2_EMMC_D2,
- GPIO2A2_SFC_WP_IO2,
-
- GPIO2A1_SHIFT = 2,
- GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
- GPIO2A1_GPIO = 0,
- GPIO2A1_FLASH_D1,
- GPIO2A1_EMMC_D1,
- GPIO2A1_SFC_SO_IO1,
-
- GPIO2A0_SHIFT = 0,
- GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
- GPIO2A0_GPIO = 0,
- GPIO2A0_FLASH_D0,
- GPIO2A0_EMMC_D0,
- GPIO2A0_SFC_SI_IO0,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
- GPIO2B7_SHIFT = 14,
- GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
- GPIO2B7_GPIO = 0,
- GPIO2B7_FLASH_CS1,
- GPIO2B7_SFC_CLK,
-
- GPIO2B6_SHIFT = 12,
- GPIO2B6_MASK = 1 << GPIO2B6_SHIFT,
- GPIO2B6_GPIO = 0,
- GPIO2B6_EMMC_CLKO,
-
- GPIO2B5_SHIFT = 10,
- GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
- GPIO2B5_GPIO = 0,
- GPIO2B5_FLASH_CS0,
-
- GPIO2B4_SHIFT = 8,
- GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
- GPIO2B4_GPIO = 0,
- GPIO2B4_FLASH_RDY,
- GPIO2B4_EMMC_CMD,
- GPIO2B4_SFC_CSN0,
-
- GPIO2B3_SHIFT = 6,
- GPIO2B3_MASK = 1 << GPIO2B3_SHIFT,
- GPIO2B3_GPIO = 0,
- GPIO2B3_FLASH_RDN,
-
- GPIO2B2_SHIFT = 4,
- GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
- GPIO2B2_GPIO = 0,
- GPIO2B2_FLASH_WRN,
-
- GPIO2B1_SHIFT = 2,
- GPIO2B1_MASK = 1 << GPIO2B1_SHIFT,
- GPIO2B1_GPIO = 0,
- GPIO2B1_FLASH_CLE,
-
- GPIO2B0_SHIFT = 0,
- GPIO2B0_MASK = 1 << GPIO2B0_SHIFT,
- GPIO2B0_GPIO = 0,
- GPIO2B0_FLASH_ALE,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
- GPIO2D7_SHIFT = 14,
- GPIO2D7_MASK = 1 << GPIO2D7_SHIFT,
- GPIO2D7_GPIO = 0,
- GPIO2D7_SDIO_D0,
-
- GPIO2D6_SHIFT = 12,
- GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
- GPIO2D6_GPIO = 0,
- GPIO2D6_SDIO_CMD,
-
- GPIO2D5_SHIFT = 10,
- GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
- GPIO2D5_GPIO = 0,
- GPIO2D5_SDIO_CLKO,
-
- GPIO2D4_SHIFT = 8,
- GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
- GPIO2D4_GPIO = 0,
- GPIO2D4_I2C1_SCL,
-
- GPIO2D3_SHIFT = 6,
- GPIO2D3_MASK = 1 << GPIO2D3_SHIFT,
- GPIO2D3_GPIO = 0,
- GPIO2D3_I2C1_SDA,
-
- GPIO2D2_SHIFT = 4,
- GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
- GPIO2D2_GPIO = 0,
- GPIO2D2_UART2_SOUT_M0,
- GPIO2D2_JTAG_TCK,
-
- GPIO2D1_SHIFT = 2,
- GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
- GPIO2D1_GPIO = 0,
- GPIO2D1_UART2_SIN_M0,
- GPIO2D1_JTAG_TMS,
- GPIO2D1_DSP_TMS,
-
- GPIO2D0_SHIFT = 0,
- GPIO2D0_MASK = 3,
- GPIO2D0_GPIO = 0,
- GPIO2D0_UART0_CTSN,
- GPIO2D0_SPI_CLK_M0,
- GPIO2D0_DSP_TCK,
-};
-
-/* GRF_GPIO3A_IOMUX */
-enum {
- GPIO3A7_SHIFT = 14,
- GPIO3A7_MASK = 1 << GPIO3A7_SHIFT,
- GPIO3A7_GPIO = 0,
-
- GPIO3A6_SHIFT = 12,
- GPIO3A6_MASK = 1 << GPIO3A6_SHIFT,
- GPIO3A6_GPIO = 0,
- GPIO3A6_UART1_SOUT,
-
- GPIO3A5_SHIFT = 10,
- GPIO3A5_MASK = 1 << GPIO3A5_SHIFT,
- GPIO3A5_GPIO = 0,
- GPIO3A5_UART1_SIN,
-
- GPIO3A4_SHIFT = 8,
- GPIO3A4_MASK = 1 << GPIO3A4_SHIFT,
- GPIO3A4_GPIO = 0,
- GPIO3A4_UART1_CTSN,
-
- GPIO3A3_SHIFT = 6,
- GPIO3A3_MASK = 1 << GPIO3A3_SHIFT,
- GPIO3A3_GPIO = 0,
- GPIO3A3_UART1_RTSN,
-
- GPIO3A2_SHIFT = 4,
- GPIO3A2_MASK = 1 << GPIO3A2_SHIFT,
- GPIO3A2_GPIO = 0,
- GPIO3A2_SDIO_D3,
-
- GPIO3A1_SHIFT = 2,
- GPIO3A1_MASK = 1 << GPIO3A1_SHIFT,
- GPIO3A1_GPIO = 0,
- GPIO3A1_SDIO_D2,
-
- GPIO3A0_SHIFT = 0,
- GPIO3A0_MASK = 1,
- GPIO3A0_GPIO = 0,
- GPIO3A0_SDIO_D1,
-};
-
-/* GRF_GPIO3C_IOMUX */
-enum {
- GPIO3C7_SHIFT = 14,
- GPIO3C7_MASK = 1 << GPIO3C7_SHIFT,
- GPIO3C7_GPIO = 0,
- GPIO3C7_CIF_CLKI,
-
- GPIO3C6_SHIFT = 12,
- GPIO3C6_MASK = 1 << GPIO3C6_SHIFT,
- GPIO3C6_GPIO = 0,
- GPIO3C6_CIF_VSYNC,
-
- GPIO3C5_SHIFT = 10,
- GPIO3C5_MASK = 1 << GPIO3C5_SHIFT,
- GPIO3C5_GPIO = 0,
- GPIO3C5_SDMMC_CMD,
-
- GPIO3C4_SHIFT = 8,
- GPIO3C4_MASK = 1 << GPIO3C4_SHIFT,
- GPIO3C4_GPIO = 0,
- GPIO3C4_SDMMC_CLKO,
-
- GPIO3C3_SHIFT = 6,
- GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
- GPIO3C3_GPIO = 0,
- GPIO3C3_SDMMC_D0,
- GPIO3C3_UART2_SOUT_M1,
-
- GPIO3C2_SHIFT = 4,
- GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
- GPIO3C2_GPIO = 0,
- GPIO3C2_SDMMC_D1,
- GPIO3C2_UART2_SIN_M1,
-
- GPIOC1_SHIFT = 2,
- GPIOC1_MASK = 1 << GPIOC1_SHIFT,
- GPIOC1_GPIO = 0,
- GPIOC1_SDMMC_D2,
-
- GPIOC0_SHIFT = 0,
- GPIOC0_MASK = 1,
- GPIO3C0_GPIO = 0,
- GPIO3C0_SDMMC_D3,
-};
-
-static void pinctrl_rv1108_uart_config(struct rv1108_grf *grf, int uart_id)
-{
- switch (uart_id) {
- case PERIPH_ID_UART0:
- rk_clrsetreg(&grf->gpio3a_iomux,
- GPIO3A6_MASK | GPIO3A5_MASK,
- GPIO3A6_UART1_SOUT << GPIO3A6_SHIFT |
- GPIO3A5_UART1_SIN << GPIO3A5_SHIFT);
- break;
- case PERIPH_ID_UART1:
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D3_MASK | GPIO1D2_MASK | GPIO1D1_MASK |
- GPIO1D0_MASK,
- GPIO1D3_UART0_SOUT << GPIO1D3_SHIFT |
- GPIO1D2_UART0_SIN << GPIO1D2_SHIFT |
- GPIO1D1_UART0_RTSN << GPIO1D1_SHIFT |
- GPIO1D0_UART0_CTSN << GPIO1D0_SHIFT);
- break;
- case PERIPH_ID_UART2:
- rk_clrsetreg(&grf->gpio2d_iomux,
- GPIO2D2_MASK | GPIO2D1_MASK,
- GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
- GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
- break;
- }
-}
-
-static void pinctrl_rv1108_gmac_config(struct rv1108_grf *grf, int func)
-{
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B7_MASK | GPIO1B6_MASK | GPIO1B5_MASK |
- GPIO1B4_MASK | GPIO1B3_MASK | GPIO1B2_MASK,
- GPIO1B7_GMAC_RXDV << GPIO1B7_SHIFT |
- GPIO1B6_GMAC_RXD1 << GPIO1B6_SHIFT |
- GPIO1B5_GMAC_RXD0 << GPIO1B5_SHIFT |
- GPIO1B4_GMAC_TXEN << GPIO1B4_SHIFT |
- GPIO1B3_GMAC_TXD1 << GPIO1B3_SHIFT |
- GPIO1B2_GMAC_TXD0 << GPIO1B2_SHIFT);
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C5_MASK | GPIO1C4_MASK |
- GPIO1C3_MASK | GPIO1C2_MASK,
- GPIO1C5_GMAC_CLK << GPIO1C5_SHIFT |
- GPIO1C4_GMAC_MDC << GPIO1C4_SHIFT |
- GPIO1C3_GMAC_MDIO << GPIO1C3_SHIFT |
- GPIO1C2_GMAC_RXER << GPIO1C2_SHIFT);
- writel(0xffff57f5, &grf->gpio1b_drv);
-}
-
-static void pinctrl_rv1108_sfc_config(struct rv1108_grf *grf)
-{
- rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A3_MASK | GPIO2A2_MASK |
- GPIO2A1_MASK | GPIO2A0_MASK,
- GPIO2A3_SFC_HOLD_IO3 << GPIO2A3_SHIFT |
- GPIO2A2_SFC_WP_IO2 << GPIO2A2_SHIFT |
- GPIO2A1_SFC_SO_IO1 << GPIO2A1_SHIFT |
- GPIO2A0_SFC_SI_IO0 << GPIO2A0_SHIFT);
- rk_clrsetreg(&grf->gpio2b_iomux, GPIO2B7_MASK | GPIO2B4_MASK,
- GPIO2B7_SFC_CLK << GPIO2B7_SHIFT |
- GPIO2B4_SFC_CSN0 << GPIO2B4_SHIFT);
-}
-
-static int rv1108_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
-
- switch (func) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- pinctrl_rv1108_uart_config(priv->grf, func);
- break;
- case PERIPH_ID_GMAC:
- pinctrl_rv1108_gmac_config(priv->grf, func);
- case PERIPH_ID_SFC:
- pinctrl_rv1108_sfc_config(priv->grf);
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rv1108_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
- u32 cell[3];
- int ret;
-
- ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 11:
- return PERIPH_ID_SDCARD;
- case 13:
- return PERIPH_ID_EMMC;
- case 19:
- return PERIPH_ID_GMAC;
- case 30:
- return PERIPH_ID_I2C0;
- case 31:
- return PERIPH_ID_I2C1;
- case 32:
- return PERIPH_ID_I2C2;
- case 39:
- return PERIPH_ID_PWM0;
- case 44:
- return PERIPH_ID_UART0;
- case 45:
- return PERIPH_ID_UART1;
- case 46:
- return PERIPH_ID_UART2;
- case 56:
- return PERIPH_ID_SFC;
- }
-
- return -ENOENT;
-}
-
-static int rv1108_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rv1108_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
-
- return rv1108_pinctrl_request(dev, func, 0);
-}
-
-static struct pinctrl_ops rv1108_pinctrl_ops = {
- .set_state_simple = rv1108_pinctrl_set_state_simple,
- .request = rv1108_pinctrl_request,
- .get_periph_id = rv1108_pinctrl_get_periph_id,
-};
-
-static int rv1108_pinctrl_probe(struct udevice *dev)
-{
- struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-
- return 0;
-}
-
-static const struct udevice_id rv1108_pinctrl_ids[] = {
- {.compatible = "rockchip,rv1108-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rv1108) = {
- .name = "pinctrl_rv1108",
- .id = UCLASS_PINCTRL,
- .of_match = rv1108_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rv1108_pinctrl_priv),
- .ops = &rv1108_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
- .probe = rv1108_pinctrl_probe,
-};
git.openpandora.org / pandora-u-boot.git / commitdiff