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MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.
authorKevin Cernekee <cernekee@gmail.com>
Sat, 19 Sep 2009 02:12:45 +0000 (19:12 -0700)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 30 Sep 2009 19:47:00 +0000 (21:47 +0200)
This extends commit a8ca8b64e3fdfec17679cba0ca5ce6e3ffed092d to cover
MIPSxx-style board cache code.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

No differences found
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