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drm/i915: Set aux clk to 100MHz for Valleyview
authorVijay Purushothaman <vijay.a.purushothaman@intel.com>
Thu, 27 Sep 2012 13:43:01 +0000 (19:13 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 28 Sep 2012 14:42:52 +0000 (16:42 +0200)
Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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