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OMAP3: PM: Clear the SCTLR C bit in asm code to prevent data cache allocation
authorSantosh Shilimkar <santosh.shilimkar@ti.com>
Sun, 23 Jan 2011 17:21:09 +0000 (22:51 +0530)
committerKevin Hilman <khilman@ti.com>
Thu, 10 Mar 2011 20:23:13 +0000 (12:23 -0800)
On the newer ARM processors like CortexA8, CortexA9, the caches can be
speculatively loaded while they are getting flushed.

Clear the SCTLR C bit to prevent further data cache allocation as
part of cache clean routine

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>

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