--- /dev/null
+diff -uNr linux-2.6.20.vanilla/arch/arm/configs/simpad_defconfig linux-2.6.20/arch/arm/configs/simpad_defconfig
+--- linux-2.6.20.vanilla/arch/arm/configs/simpad_defconfig 2007-02-10 19:01:14.000000000 +0100
++++ linux-2.6.20/arch/arm/configs/simpad_defconfig 2007-02-11 16:39:39.000000000 +0100
+@@ -1,75 +1,121 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.12-rc1-bk2
+-# Mon Mar 28 00:10:36 2005
++# Linux kernel version: 2.6.19.1
++# Tue Jan 2 22:07:26 2007
+ #
+ CONFIG_ARM=y
++# CONFIG_GENERIC_TIME is not set
+ CONFIG_MMU=y
+-CONFIG_UID16=y
++CONFIG_GENERIC_HARDIRQS=y
++CONFIG_TRACE_IRQFLAGS_SUPPORT=y
++CONFIG_HARDIRQS_SW_RESEND=y
++CONFIG_GENERIC_IRQ_PROBE=y
+ CONFIG_RWSEM_GENERIC_SPINLOCK=y
++CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
+-CONFIG_GENERIC_IOMAP=y
++CONFIG_ARCH_MTD_XIP=y
++CONFIG_VECTORS_BASE=0xffff0000
++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+ #
+ # Code maturity level options
+ #
+ CONFIG_EXPERIMENTAL=y
+-CONFIG_CLEAN_COMPILE=y
+ CONFIG_BROKEN_ON_SMP=y
+ CONFIG_LOCK_KERNEL=y
++CONFIG_INIT_ENV_ARG_LIMIT=32
+
+ #
+ # General setup
+ #
+ CONFIG_LOCALVERSION="oe1"
++CONFIG_LOCALVERSION_AUTO=y
+ CONFIG_SWAP=y
+ CONFIG_SYSVIPC=y
++# CONFIG_IPC_NS is not set
+ # CONFIG_POSIX_MQUEUE is not set
+ # CONFIG_BSD_PROCESS_ACCT is not set
+-CONFIG_SYSCTL=y
++# CONFIG_TASKSTATS is not set
++# CONFIG_UTS_NS is not set
+ # CONFIG_AUDIT is not set
+-CONFIG_HOTPLUG=y
+-CONFIG_KOBJECT_UEVENT=y
+ # CONFIG_IKCONFIG is not set
++# CONFIG_RELAY is not set
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SYSCTL=y
+ CONFIG_EMBEDDED=y
++CONFIG_UID16=y
++CONFIG_SYSCTL_SYSCALL=y
+ CONFIG_KALLSYMS=y
+ CONFIG_KALLSYMS_ALL=y
+ CONFIG_KALLSYMS_EXTRA_PASS=y
++CONFIG_HOTPLUG=y
++CONFIG_PRINTK=y
++CONFIG_BUG=y
++CONFIG_ELF_CORE=y
+ CONFIG_BASE_FULL=y
+ CONFIG_FUTEX=y
+ CONFIG_EPOLL=y
+-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+ CONFIG_SHMEM=y
+-CONFIG_CC_ALIGN_FUNCTIONS=0
+-CONFIG_CC_ALIGN_LABELS=0
+-CONFIG_CC_ALIGN_LOOPS=0
+-CONFIG_CC_ALIGN_JUMPS=0
++CONFIG_SLAB=y
++CONFIG_VM_EVENT_COUNTERS=y
++CONFIG_RT_MUTEXES=y
+ # CONFIG_TINY_SHMEM is not set
+ CONFIG_BASE_SMALL=0
++# CONFIG_SLOB is not set
+
+ #
+ # Loadable module support
+ #
+ CONFIG_MODULES=y
+ # CONFIG_MODULE_UNLOAD is not set
+-CONFIG_OBSOLETE_MODPARM=y
+ # CONFIG_MODVERSIONS is not set
+ # CONFIG_MODULE_SRCVERSION_ALL is not set
+ CONFIG_KMOD=y
+
+ #
++# Block layer
++#
++CONFIG_BLOCK=y
++# CONFIG_BLK_DEV_IO_TRACE is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_DEFAULT_AS is not set
++# CONFIG_DEFAULT_DEADLINE is not set
++CONFIG_DEFAULT_CFQ=y
++# CONFIG_DEFAULT_NOOP is not set
++CONFIG_DEFAULT_IOSCHED="cfq"
++
++#
+ # System Type
+ #
++# CONFIG_ARCH_AAEC2000 is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_REALVIEW is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_AT91 is not set
+ # CONFIG_ARCH_CLPS7500 is not set
+ # CONFIG_ARCH_CLPS711X is not set
+ # CONFIG_ARCH_CO285 is not set
+ # CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_EP93XX is not set
+ # CONFIG_ARCH_FOOTBRIDGE is not set
+-# CONFIG_ARCH_INTEGRATOR is not set
+-# CONFIG_ARCH_IOP3XX is not set
++# CONFIG_ARCH_NETX is not set
++# CONFIG_ARCH_H720X is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_IOP32X is not set
++# CONFIG_ARCH_IOP33X is not set
+ # CONFIG_ARCH_IXP4XX is not set
+ # CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_IXP23XX is not set
+ # CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_PNX4008 is not set
+ # CONFIG_ARCH_PXA is not set
+ # CONFIG_ARCH_RPC is not set
+ CONFIG_ARCH_SA1100=y
+@@ -77,9 +123,6 @@
+ # CONFIG_ARCH_SHARK is not set
+ # CONFIG_ARCH_LH7A40X is not set
+ # CONFIG_ARCH_OMAP is not set
+-# CONFIG_ARCH_VERSATILE is not set
+-# CONFIG_ARCH_IMX is not set
+-# CONFIG_ARCH_H720X is not set
+
+ #
+ # SA11x0 Implementations
+@@ -109,11 +152,14 @@
+ CONFIG_CPU_CACHE_V4WB=y
+ CONFIG_CPU_CACHE_VIVT=y
+ CONFIG_CPU_TLB_V4WB=y
+-CONFIG_CPU_MINICACHE=y
++CONFIG_CPU_CP15=y
++CONFIG_CPU_CP15_MMU=y
+
+ #
+ # Processor Features
+ #
++# CONFIG_CPU_ICACHE_DISABLE is not set
++# CONFIG_CPU_DCACHE_DISABLE is not set
+
+ #
+ # Bus support
+@@ -126,6 +172,8 @@
+ CONFIG_PCCARD=y
+ # CONFIG_PCMCIA_DEBUG is not set
+ CONFIG_PCMCIA=y
++CONFIG_PCMCIA_LOAD_CIS=y
++CONFIG_PCMCIA_IOCTL=y
+
+ #
+ # PC-card bridges
+@@ -138,7 +186,21 @@
+ # Kernel Features
+ #
+ CONFIG_PREEMPT=y
++# CONFIG_NO_IDLE_HZ is not set
++CONFIG_HZ=100
++# CONFIG_AEABI is not set
++CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
++CONFIG_NODES_SHIFT=2
++CONFIG_SELECT_MEMORY_MODEL=y
++# CONFIG_FLATMEM_MANUAL is not set
++CONFIG_DISCONTIGMEM_MANUAL=y
++# CONFIG_SPARSEMEM_MANUAL is not set
+ CONFIG_DISCONTIGMEM=y
++CONFIG_FLAT_NODE_MEM_MAP=y
++CONFIG_NEED_MULTIPLE_NODES=y
++# CONFIG_SPARSEMEM_STATIC is not set
++CONFIG_SPLIT_PTLOCK_CPUS=4096
++# CONFIG_RESOURCES_64BIT is not set
+ CONFIG_LEDS=y
+ CONFIG_LEDS_TIMER=y
+ # CONFIG_LEDS_CPU is not set
+@@ -181,9 +243,161 @@
+ #
+ CONFIG_PM=y
+ # CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++# CONFIG_PM_SYSFS_DEPRECATED is not set
+ CONFIG_APM=y
+
+ #
++# Networking
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++# CONFIG_NETDEBUG is not set
++CONFIG_PACKET=y
++CONFIG_PACKET_MMAP=y
++CONFIG_UNIX=y
++CONFIG_XFRM=y
++# CONFIG_XFRM_USER is not set
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_FIB_HASH=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_XFRM_TUNNEL is not set
++# CONFIG_INET_TUNNEL is not set
++CONFIG_INET_XFRM_MODE_TRANSPORT=y
++CONFIG_INET_XFRM_MODE_TUNNEL=y
++CONFIG_INET_XFRM_MODE_BEET=y
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
++# CONFIG_TCP_CONG_ADVANCED is not set
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_DEFAULT_TCP_CONG="cubic"
++# CONFIG_IPV6 is not set
++# CONFIG_INET6_XFRM_TUNNEL is not set
++# CONFIG_INET6_TUNNEL is not set
++# CONFIG_NETWORK_SECMARK is not set
++# CONFIG_NETFILTER is not set
++
++#
++# DCCP Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_DCCP is not set
++
++#
++# SCTP Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_SCTP is not set
++
++#
++# TIPC Configuration (EXPERIMENTAL)
++#
++# CONFIG_TIPC is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++
++#
++# QoS and/or fair queueing
++#
++# CONFIG_NET_SCHED is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_HAMRADIO is not set
++CONFIG_IRDA=m
++
++#
++# IrDA protocols
++#
++CONFIG_IRLAN=m
++CONFIG_IRNET=m
++CONFIG_IRCOMM=m
++# CONFIG_IRDA_ULTRA is not set
++
++#
++# IrDA options
++#
++# CONFIG_IRDA_CACHE_LAST_LSAP is not set
++# CONFIG_IRDA_FAST_RR is not set
++# CONFIG_IRDA_DEBUG is not set
++
++#
++# Infrared-port device drivers
++#
++
++#
++# SIR device drivers
++#
++CONFIG_IRTTY_SIR=m
++
++#
++# Dongle support
++#
++# CONFIG_DONGLE is not set
++
++#
++# Old SIR device drivers
++#
++CONFIG_IRPORT_SIR=m
++
++#
++# Old Serial dongle support
++#
++# CONFIG_DONGLE_OLD is not set
++
++#
++# FIR device drivers
++#
++CONFIG_SA1100_FIR=m
++CONFIG_BT=m
++CONFIG_BT_L2CAP=m
++CONFIG_BT_SCO=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++# CONFIG_BT_HIDP is not set
++
++#
++# Bluetooth device drivers
++#
++# CONFIG_BT_HCIUART is not set
++# CONFIG_BT_HCIDTL1 is not set
++# CONFIG_BT_HCIBT3C is not set
++# CONFIG_BT_HCIBLUECARD is not set
++# CONFIG_BT_HCIBTUART is not set
++# CONFIG_BT_HCIVHCI is not set
++# CONFIG_IEEE80211 is not set
++CONFIG_WIRELESS_EXT=y
++
++#
+ # Device Drivers
+ #
+
+@@ -192,8 +406,14 @@
+ #
+ CONFIG_STANDALONE=y
+ CONFIG_PREVENT_FIRMWARE_BUILD=y
+-CONFIG_FW_LOADER=m
++CONFIG_FW_LOADER=y
+ # CONFIG_DEBUG_DRIVER is not set
++# CONFIG_SYS_HYPERVISOR is not set
++
++#
++# Connector - unified userspace <-> kernelspace linker
++#
++# CONFIG_CONNECTOR is not set
+
+ #
+ # Memory Technology Devices (MTD)
+@@ -214,6 +434,8 @@
+ # CONFIG_FTL is not set
+ # CONFIG_NFTL is not set
+ # CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
+
+ #
+ # RAM/ROM/Flash chip drivers
+@@ -236,6 +458,7 @@
+ # CONFIG_MTD_CFI_I2 is not set
+ # CONFIG_MTD_CFI_I4 is not set
+ # CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_OTP is not set
+ CONFIG_MTD_CFI_INTELEXT=y
+ # CONFIG_MTD_CFI_AMDSTD is not set
+ # CONFIG_MTD_CFI_STAA is not set
+@@ -243,6 +466,7 @@
+ CONFIG_MTD_RAM=y
+ # CONFIG_MTD_ROM is not set
+ # CONFIG_MTD_ABSENT is not set
++# CONFIG_MTD_OBSOLETE_CHIPS is not set
+ # CONFIG_MTD_XIP is not set
+
+ #
+@@ -252,8 +476,8 @@
+ # CONFIG_MTD_PHYSMAP is not set
+ # CONFIG_MTD_ARM_INTEGRATOR is not set
+ CONFIG_MTD_SA1100=y
+-# CONFIG_MTD_EDB7312 is not set
+ # CONFIG_MTD_IMPA7 is not set
++# CONFIG_MTD_PLATRAM is not set
+
+ #
+ # Self-contained MTD device drivers
+@@ -261,7 +485,6 @@
+ # CONFIG_MTD_SLRAM is not set
+ # CONFIG_MTD_PHRAM is not set
+ # CONFIG_MTD_MTDRAM is not set
+-# CONFIG_MTD_BLKMTD is not set
+ # CONFIG_MTD_BLOCK2MTD is not set
+
+ #
+@@ -277,6 +500,11 @@
+ # CONFIG_MTD_NAND is not set
+
+ #
++# OneNAND Flash Device Drivers
++#
++# CONFIG_MTD_ONENAND is not set
++
++#
+ # Parallel port support
+ #
+ # CONFIG_PARPORT is not set
+@@ -289,8 +517,6 @@
+ #
+ # Block devices
+ #
+-# CONFIG_BLK_DEV_FD is not set
+-# CONFIG_BLK_DEV_XD is not set
+ # CONFIG_BLK_DEV_COW_COMMON is not set
+ CONFIG_BLK_DEV_LOOP=m
+ # CONFIG_BLK_DEV_CRYPTOLOOP is not set
+@@ -298,16 +524,9 @@
+ CONFIG_BLK_DEV_RAM=m
+ CONFIG_BLK_DEV_RAM_COUNT=16
+ CONFIG_BLK_DEV_RAM_SIZE=8192
+-CONFIG_INITRAMFS_SOURCE=""
++CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_BLK_DEV_INITRD is not set
+ # CONFIG_CDROM_PKTCDVD is not set
+-
+-#
+-# IO Schedulers
+-#
+-CONFIG_IOSCHED_NOOP=y
+-CONFIG_IOSCHED_AS=y
+-CONFIG_IOSCHED_DEADLINE=y
+-CONFIG_IOSCHED_CFQ=y
+ # CONFIG_ATA_OVER_ETH is not set
+
+ #
+@@ -318,7 +537,14 @@
+ #
+ # SCSI device support
+ #
++# CONFIG_RAID_ATTRS is not set
+ # CONFIG_SCSI is not set
++# CONFIG_SCSI_NETLINK is not set
++
++#
++# Serial ATA (prod) and Parallel ATA (experimental) drivers
++#
++# CONFIG_ATA is not set
+
+ #
+ # Multi-device support (RAID and LVM)
+@@ -328,6 +554,7 @@
+ #
+ # Fusion MPT device support
+ #
++# CONFIG_FUSION is not set
+
+ #
+ # IEEE 1394 (FireWire) support
+@@ -338,136 +565,8 @@
+ #
+
+ #
+-# Networking support
+-#
+-CONFIG_NET=y
+-
+-#
+-# Networking options
+-#
+-CONFIG_PACKET=y
+-CONFIG_PACKET_MMAP=y
+-# CONFIG_NETLINK_DEV is not set
+-CONFIG_UNIX=y
+-# CONFIG_NET_KEY is not set
+-CONFIG_INET=y
+-# CONFIG_IP_MULTICAST is not set
+-# CONFIG_IP_ADVANCED_ROUTER is not set
+-CONFIG_IP_PNP=y
+-CONFIG_IP_PNP_DHCP=y
+-CONFIG_IP_PNP_BOOTP=y
+-# CONFIG_IP_PNP_RARP is not set
+-# CONFIG_NET_IPIP is not set
+-# CONFIG_NET_IPGRE is not set
+-# CONFIG_ARPD is not set
+-# CONFIG_SYN_COOKIES is not set
+-# CONFIG_INET_AH is not set
+-# CONFIG_INET_ESP is not set
+-# CONFIG_INET_IPCOMP is not set
+-# CONFIG_INET_TUNNEL is not set
+-# CONFIG_IP_TCPDIAG is not set
+-# CONFIG_IP_TCPDIAG_IPV6 is not set
+-# CONFIG_IPV6 is not set
+-# CONFIG_NETFILTER is not set
+-
+-#
+-# SCTP Configuration (EXPERIMENTAL)
+-#
+-# CONFIG_IP_SCTP is not set
+-# CONFIG_ATM is not set
+-# CONFIG_BRIDGE is not set
+-# CONFIG_VLAN_8021Q is not set
+-# CONFIG_DECNET is not set
+-# CONFIG_LLC2 is not set
+-# CONFIG_IPX is not set
+-# CONFIG_ATALK is not set
+-# CONFIG_X25 is not set
+-# CONFIG_LAPB is not set
+-# CONFIG_NET_DIVERT is not set
+-# CONFIG_ECONET is not set
+-# CONFIG_WAN_ROUTER is not set
+-
+-#
+-# QoS and/or fair queueing
+-#
+-# CONFIG_NET_SCHED is not set
+-# CONFIG_NET_CLS_ROUTE is not set
+-
+-#
+-# Network testing
+-#
+-# CONFIG_NET_PKTGEN is not set
+-# CONFIG_NETPOLL is not set
+-# CONFIG_NET_POLL_CONTROLLER is not set
+-# CONFIG_HAMRADIO is not set
+-CONFIG_IRDA=m
+-
+-#
+-# IrDA protocols
+-#
+-CONFIG_IRLAN=m
+-CONFIG_IRNET=m
+-CONFIG_IRCOMM=m
+-# CONFIG_IRDA_ULTRA is not set
+-
+-#
+-# IrDA options
+-#
+-# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+-# CONFIG_IRDA_FAST_RR is not set
+-# CONFIG_IRDA_DEBUG is not set
+-
+-#
+-# Infrared-port device drivers
+-#
+-
++# Network device support
+ #
+-# SIR device drivers
+-#
+-CONFIG_IRTTY_SIR=m
+-
+-#
+-# Dongle support
+-#
+-# CONFIG_DONGLE is not set
+-
+-#
+-# Old SIR device drivers
+-#
+-CONFIG_IRPORT_SIR=m
+-
+-#
+-# Old Serial dongle support
+-#
+-# CONFIG_DONGLE_OLD is not set
+-
+-#
+-# FIR device drivers
+-#
+-# CONFIG_NSC_FIR is not set
+-# CONFIG_WINBOND_FIR is not set
+-# CONFIG_SMC_IRCC_FIR is not set
+-# CONFIG_ALI_FIR is not set
+-CONFIG_SA1100_FIR=m
+-CONFIG_BT=m
+-CONFIG_BT_L2CAP=m
+-CONFIG_BT_SCO=m
+-CONFIG_BT_RFCOMM=m
+-CONFIG_BT_RFCOMM_TTY=y
+-CONFIG_BT_BNEP=m
+-CONFIG_BT_BNEP_MC_FILTER=y
+-CONFIG_BT_BNEP_PROTO_FILTER=y
+-# CONFIG_BT_HIDP is not set
+-
+-#
+-# Bluetooth device drivers
+-#
+-# CONFIG_BT_HCIUART is not set
+-# CONFIG_BT_HCIDTL1 is not set
+-# CONFIG_BT_HCIBT3C is not set
+-# CONFIG_BT_HCIBLUECARD is not set
+-# CONFIG_BT_HCIBTUART is not set
+-# CONFIG_BT_HCIVHCI is not set
+ CONFIG_NETDEVICES=y
+ CONFIG_DUMMY=y
+ # CONFIG_BONDING is not set
+@@ -480,14 +579,19 @@
+ # CONFIG_ARCNET is not set
+
+ #
++# PHY device support
++#
++# CONFIG_PHYLIB is not set
++
++#
+ # Ethernet (10 or 100Mbit)
+ #
+ CONFIG_NET_ETHERNET=y
+ CONFIG_MII=m
+ # CONFIG_NET_VENDOR_3COM is not set
+-# CONFIG_LANCE is not set
+ # CONFIG_NET_VENDOR_SMC is not set
+ # CONFIG_SMC91X is not set
++# CONFIG_DM9000 is not set
+ # CONFIG_NET_VENDOR_RACAL is not set
+ # CONFIG_AT1700 is not set
+ # CONFIG_DEPCA is not set
+@@ -497,7 +601,6 @@
+ # CONFIG_AC3200 is not set
+ # CONFIG_APRICOT is not set
+ # CONFIG_CS89x0 is not set
+-# CONFIG_NET_POCKET is not set
+
+ #
+ # Ethernet (1000 Mbit)
+@@ -516,6 +619,7 @@
+ # Wireless LAN (non-hamradio)
+ #
+ CONFIG_NET_RADIO=y
++# CONFIG_NET_WIRELESS_RTNETLINK is not set
+
+ #
+ # Obsolete Wireless cards support (pre-802.11)
+@@ -542,6 +646,7 @@
+ #
+ # CONFIG_AIRO_CS is not set
+ # CONFIG_PCMCIA_WL3501 is not set
++# CONFIG_HOSTAP is not set
+ CONFIG_NET_WIRELESS=y
+
+ #
+@@ -568,10 +673,14 @@
+ CONFIG_PPP_SYNC_TTY=m
+ CONFIG_PPP_DEFLATE=m
+ CONFIG_PPP_BSDCOMP=m
++# CONFIG_PPP_MPPE is not set
+ CONFIG_PPPOE=m
+ # CONFIG_SLIP is not set
++CONFIG_SLHC=m
+ # CONFIG_SHAPER is not set
+ # CONFIG_NETCONSOLE is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
+
+ #
+ # ISDN subsystem
+@@ -582,6 +691,7 @@
+ # Input device support
+ #
+ CONFIG_INPUT=y
++# CONFIG_INPUT_FF_MEMLESS is not set
+
+ #
+ # Userland interfaces
+@@ -614,7 +724,6 @@
+ # CONFIG_SERIO_LIBPS2 is not set
+ # CONFIG_SERIO_RAW is not set
+ # CONFIG_GAMEPORT is not set
+-CONFIG_SOUND_GAMEPORT=y
+
+ #
+ # Character devices
+@@ -622,6 +731,7 @@
+ CONFIG_VT=y
+ CONFIG_VT_CONSOLE=y
+ CONFIG_HW_CONSOLE=y
++# CONFIG_VT_HW_CONSOLE_BINDING is not set
+ # CONFIG_SERIAL_NONSTANDARD is not set
+
+ #
+@@ -649,20 +759,21 @@
+ # Watchdog Cards
+ #
+ # CONFIG_WATCHDOG is not set
++CONFIG_HW_RANDOM=y
+ # CONFIG_NVRAM is not set
+-# CONFIG_RTC is not set
+ # CONFIG_DTLK is not set
+ # CONFIG_R3964 is not set
+
+ #
+ # Ftape, the floppy tape device driver
+ #
+-# CONFIG_DRM is not set
+
+ #
+ # PCMCIA character devices
+ #
+ # CONFIG_SYNCLINK_CS is not set
++# CONFIG_CARDMAN_4000 is not set
++# CONFIG_CARDMAN_4040 is not set
+ # CONFIG_RAW_DRIVER is not set
+
+ #
+@@ -676,8 +787,48 @@
+ # CONFIG_I2C is not set
+
+ #
++# SPI support
++#
++# CONFIG_SPI is not set
++# CONFIG_SPI_MASTER is not set
++
++#
++# Dallas's 1-wire bus
++#
++# CONFIG_W1 is not set
++
++#
++# Hardware Monitoring support
++#
++CONFIG_HWMON=y
++# CONFIG_HWMON_VID is not set
++# CONFIG_SENSORS_ABITUGURU is not set
++# CONFIG_SENSORS_F71805F is not set
++# CONFIG_SENSORS_VT1211 is not set
++# CONFIG_HWMON_DEBUG_CHIP is not set
++
++#
+ # Misc devices
+ #
++# CONFIG_TIFM_CORE is not set
++
++#
++# Multimedia Capabilities Port drivers
++#
++# CONFIG_MCP_SA11X0 is not set
++
++#
++# LED devices
++#
++# CONFIG_NEW_LEDS is not set
++
++#
++# LED drivers
++#
++
++#
++# LED Triggers
++#
+
+ #
+ # Multimedia devices
+@@ -692,14 +843,18 @@
+ #
+ # Graphics support
+ #
++CONFIG_FIRMWARE_EDID=y
+ CONFIG_FB=y
+-# CONFIG_FB_CFB_FILLRECT is not set
+-# CONFIG_FB_CFB_COPYAREA is not set
+-# CONFIG_FB_CFB_IMAGEBLIT is not set
+-# CONFIG_FB_SOFT_CURSOR is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
+ # CONFIG_FB_MODE_HELPERS is not set
+ # CONFIG_FB_TILEBLITTING is not set
+ # CONFIG_FB_SA1100 is not set
++# CONFIG_FB_S1D13XXX is not set
++CONFIG_FB_MQ200=y
+ # CONFIG_FB_VIRTUAL is not set
+
+ #
+@@ -709,6 +864,7 @@
+ # CONFIG_MDA_CONSOLE is not set
+ CONFIG_DUMMY_CONSOLE=y
+ CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+ # CONFIG_FONTS is not set
+ CONFIG_FONT_8x8=y
+ CONFIG_FONT_8x16=y
+@@ -742,9 +898,14 @@
+ #
+ CONFIG_USB_ARCH_HAS_HCD=y
+ # CONFIG_USB_ARCH_HAS_OHCI is not set
++# CONFIG_USB_ARCH_HAS_EHCI is not set
+ # CONFIG_USB is not set
+
+ #
++# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
++#
++
++#
+ # USB Gadget Support
+ #
+ # CONFIG_USB_GADGET is not set
+@@ -755,14 +916,22 @@
+ # CONFIG_MMC is not set
+
+ #
++# Real Time Clock
++#
++CONFIG_RTC_LIB=y
++# CONFIG_RTC_CLASS is not set
++
++#
+ # File systems
+ #
+ CONFIG_EXT2_FS=m
+ # CONFIG_EXT2_FS_XATTR is not set
++# CONFIG_EXT2_FS_XIP is not set
+ CONFIG_EXT3_FS=m
+ CONFIG_EXT3_FS_XATTR=y
+ # CONFIG_EXT3_FS_POSIX_ACL is not set
+ # CONFIG_EXT3_FS_SECURITY is not set
++# CONFIG_EXT4DEV_FS is not set
+ CONFIG_JBD=m
+ # CONFIG_JBD_DEBUG is not set
+ CONFIG_FS_MBCACHE=m
+@@ -771,17 +940,19 @@
+ CONFIG_REISERFS_PROC_INFO=y
+ # CONFIG_REISERFS_FS_XATTR is not set
+ # CONFIG_JFS_FS is not set
+-
+-#
+-# XFS support
+-#
++# CONFIG_FS_POSIX_ACL is not set
+ # CONFIG_XFS_FS is not set
++# CONFIG_GFS2_FS is not set
++# CONFIG_OCFS2_FS is not set
+ # CONFIG_MINIX_FS is not set
+ # CONFIG_ROMFS_FS is not set
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
+ # CONFIG_QUOTA is not set
+ CONFIG_DNOTIFY=y
+ # CONFIG_AUTOFS_FS is not set
+ # CONFIG_AUTOFS4_FS is not set
++# CONFIG_FUSE_FS is not set
+
+ #
+ # CD-ROM/DVD Filesystems
+@@ -803,14 +974,12 @@
+ # Pseudo filesystems
+ #
+ CONFIG_PROC_FS=y
++CONFIG_PROC_SYSCTL=y
+ CONFIG_SYSFS=y
+-CONFIG_DEVFS_FS=y
+-CONFIG_DEVFS_MOUNT=y
+-# CONFIG_DEVFS_DEBUG is not set
+-# CONFIG_DEVPTS_FS_XATTR is not set
+ # CONFIG_TMPFS is not set
+ # CONFIG_HUGETLB_PAGE is not set
+ CONFIG_RAMFS=y
++# CONFIG_CONFIGFS_FS is not set
+
+ #
+ # Miscellaneous filesystems
+@@ -827,8 +996,9 @@
+ # CONFIG_JFFS_PROC_FS is not set
+ CONFIG_JFFS2_FS=y
+ CONFIG_JFFS2_FS_DEBUG=0
+-# CONFIG_JFFS2_FS_NAND is not set
+-# CONFIG_JFFS2_FS_NOR_ECC is not set
++CONFIG_JFFS2_FS_WRITEBUFFER=y
++# CONFIG_JFFS2_SUMMARY is not set
++# CONFIG_JFFS2_FS_XATTR is not set
+ # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+ CONFIG_JFFS2_ZLIB=y
+ CONFIG_JFFS2_RTIME=y
+@@ -845,12 +1015,14 @@
+ #
+ CONFIG_NFS_FS=y
+ CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
+ # CONFIG_NFS_V4 is not set
+ # CONFIG_NFS_DIRECTIO is not set
+ # CONFIG_NFSD is not set
+ # CONFIG_ROOT_NFS is not set
+ CONFIG_LOCKD=y
+ CONFIG_LOCKD_V4=y
++CONFIG_NFS_COMMON=y
+ CONFIG_SUNRPC=y
+ # CONFIG_RPCSEC_GSS_KRB5 is not set
+ # CONFIG_RPCSEC_GSS_SPKM3 is not set
+@@ -860,6 +1032,7 @@
+ # CONFIG_NCP_FS is not set
+ # CONFIG_CODA_FS is not set
+ # CONFIG_AFS_FS is not set
++# CONFIG_9P_FS is not set
+
+ #
+ # Partition Types
+@@ -920,19 +1093,32 @@
+ # Kernel hacking
+ #
+ # CONFIG_PRINTK_TIME is not set
+-CONFIG_DEBUG_KERNEL=y
++CONFIG_ENABLE_MUST_CHECK=y
+ # CONFIG_MAGIC_SYSRQ is not set
++# CONFIG_UNUSED_SYMBOLS is not set
++CONFIG_DEBUG_KERNEL=y
+ CONFIG_LOG_BUF_SHIFT=14
++CONFIG_DETECT_SOFTLOCKUP=y
+ # CONFIG_SCHEDSTATS is not set
+ # CONFIG_DEBUG_SLAB is not set
+ CONFIG_DEBUG_PREEMPT=y
++# CONFIG_DEBUG_RT_MUTEXES is not set
++# CONFIG_RT_MUTEX_TESTER is not set
+ # CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_MUTEXES is not set
++# CONFIG_DEBUG_RWSEMS is not set
+ # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+ # CONFIG_DEBUG_KOBJECT is not set
+ CONFIG_DEBUG_BUGVERBOSE=y
+ # CONFIG_DEBUG_INFO is not set
+ # CONFIG_DEBUG_FS is not set
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_LIST is not set
+ CONFIG_FRAME_POINTER=y
++CONFIG_FORCED_INLINING=y
++# CONFIG_HEADERS_CHECK is not set
++# CONFIG_RCU_TORTURE_TEST is not set
+ CONFIG_DEBUG_USER=y
+ CONFIG_DEBUG_ERRORS=y
+ CONFIG_DEBUG_LL=y
+@@ -950,14 +1136,12 @@
+ # CONFIG_CRYPTO is not set
+
+ #
+-# Hardware crypto devices
+-#
+-
+-#
+ # Library routines
+ #
+ CONFIG_CRC_CCITT=m
++# CONFIG_CRC16 is not set
+ CONFIG_CRC32=y
+ # CONFIG_LIBCRC32C is not set
+ CONFIG_ZLIB_INFLATE=y
+ CONFIG_ZLIB_DEFLATE=y
++CONFIG_PLIST=y
+diff -uNr linux-2.6.20.vanilla/arch/arm/configs/simpad_defconfig~ linux-2.6.20/arch/arm/configs/simpad_defconfig~
+--- linux-2.6.20.vanilla/arch/arm/configs/simpad_defconfig~ 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.20/arch/arm/configs/simpad_defconfig~ 2007-02-11 16:35:19.000000000 +0100
+@@ -0,0 +1,963 @@
++#
++# Automatically generated make config: don't edit
++# Linux kernel version: 2.6.12-rc1-bk2
++# Mon Mar 28 00:10:36 2005
++#
++CONFIG_ARM=y
++CONFIG_MMU=y
++CONFIG_UID16=y
++CONFIG_RWSEM_GENERIC_SPINLOCK=y
++CONFIG_GENERIC_CALIBRATE_DELAY=y
++CONFIG_GENERIC_IOMAP=y
++
++#
++# Code maturity level options
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_CLEAN_COMPILE=y
++CONFIG_BROKEN_ON_SMP=y
++CONFIG_LOCK_KERNEL=y
++
++#
++# General setup
++#
++CONFIG_LOCALVERSION="oe1"
++CONFIG_SWAP=y
++CONFIG_SYSVIPC=y
++# CONFIG_POSIX_MQUEUE is not set
++# CONFIG_BSD_PROCESS_ACCT is not set
++CONFIG_SYSCTL=y
++# CONFIG_AUDIT is not set
++CONFIG_HOTPLUG=y
++CONFIG_KOBJECT_UEVENT=y
++# CONFIG_IKCONFIG is not set
++CONFIG_EMBEDDED=y
++CONFIG_KALLSYMS=y
++CONFIG_KALLSYMS_ALL=y
++CONFIG_KALLSYMS_EXTRA_PASS=y
++CONFIG_BASE_FULL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++CONFIG_SHMEM=y
++CONFIG_CC_ALIGN_FUNCTIONS=0
++CONFIG_CC_ALIGN_LABELS=0
++CONFIG_CC_ALIGN_LOOPS=0
++CONFIG_CC_ALIGN_JUMPS=0
++# CONFIG_TINY_SHMEM is not set
++CONFIG_BASE_SMALL=0
++
++#
++# Loadable module support
++#
++CONFIG_MODULES=y
++# CONFIG_MODULE_UNLOAD is not set
++CONFIG_OBSOLETE_MODPARM=y
++# CONFIG_MODVERSIONS is not set
++# CONFIG_MODULE_SRCVERSION_ALL is not set
++CONFIG_KMOD=y
++
++#
++# System Type
++#
++# CONFIG_ARCH_CLPS7500 is not set
++# CONFIG_ARCH_CLPS711X is not set
++# CONFIG_ARCH_CO285 is not set
++# CONFIG_ARCH_EBSA110 is not set
++# CONFIG_ARCH_FOOTBRIDGE is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_IOP3XX is not set
++# CONFIG_ARCH_IXP4XX is not set
++# CONFIG_ARCH_IXP2000 is not set
++# CONFIG_ARCH_L7200 is not set
++# CONFIG_ARCH_PXA is not set
++# CONFIG_ARCH_RPC is not set
++CONFIG_ARCH_SA1100=y
++# CONFIG_ARCH_S3C2410 is not set
++# CONFIG_ARCH_SHARK is not set
++# CONFIG_ARCH_LH7A40X is not set
++# CONFIG_ARCH_OMAP is not set
++# CONFIG_ARCH_VERSATILE is not set
++# CONFIG_ARCH_IMX is not set
++# CONFIG_ARCH_H720X is not set
++
++#
++# SA11x0 Implementations
++#
++# CONFIG_SA1100_ASSABET is not set
++# CONFIG_SA1100_CERF is not set
++# CONFIG_SA1100_COLLIE is not set
++# CONFIG_SA1100_H3100 is not set
++# CONFIG_SA1100_H3600 is not set
++# CONFIG_SA1100_H3800 is not set
++# CONFIG_SA1100_BADGE4 is not set
++# CONFIG_SA1100_JORNADA720 is not set
++# CONFIG_SA1100_HACKKIT is not set
++# CONFIG_SA1100_LART is not set
++# CONFIG_SA1100_PLEB is not set
++# CONFIG_SA1100_SHANNON is not set
++CONFIG_SA1100_SIMPAD=y
++# CONFIG_SA1100_SSP is not set
++
++#
++# Processor Type
++#
++CONFIG_CPU_32=y
++CONFIG_CPU_SA1100=y
++CONFIG_CPU_32v4=y
++CONFIG_CPU_ABRT_EV4=y
++CONFIG_CPU_CACHE_V4WB=y
++CONFIG_CPU_CACHE_VIVT=y
++CONFIG_CPU_TLB_V4WB=y
++CONFIG_CPU_MINICACHE=y
++
++#
++# Processor Features
++#
++
++#
++# Bus support
++#
++CONFIG_ISA=y
++
++#
++# PCCARD (PCMCIA/CardBus) support
++#
++CONFIG_PCCARD=y
++# CONFIG_PCMCIA_DEBUG is not set
++CONFIG_PCMCIA=y
++
++#
++# PC-card bridges
++#
++# CONFIG_I82365 is not set
++# CONFIG_TCIC is not set
++CONFIG_PCMCIA_SA1100=y
++
++#
++# Kernel Features
++#
++CONFIG_PREEMPT=y
++CONFIG_DISCONTIGMEM=y
++CONFIG_LEDS=y
++CONFIG_LEDS_TIMER=y
++# CONFIG_LEDS_CPU is not set
++CONFIG_ALIGNMENT_TRAP=y
++
++#
++# Boot options
++#
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="mtdparts=sa1100:512k(boot),1m(kernel),-(root) console=ttySA0 root=1f02 noinitrd mem=64M jffs2_orphaned_inodes=delete rootfstype=jffs2"
++# CONFIG_XIP_KERNEL is not set
++
++#
++# CPU Frequency scaling
++#
++# CONFIG_CPU_FREQ is not set
++
++#
++# Floating point emulation
++#
++
++#
++# At least one emulation must be selected
++#
++CONFIG_FPE_NWFPE=y
++# CONFIG_FPE_NWFPE_XP is not set
++# CONFIG_FPE_FASTFPE is not set
++
++#
++# Userspace binary formats
++#
++CONFIG_BINFMT_ELF=y
++# CONFIG_BINFMT_AOUT is not set
++CONFIG_BINFMT_MISC=m
++# CONFIG_ARTHUR is not set
++
++#
++# Power management options
++#
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++CONFIG_APM=y
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_STANDALONE=y
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++CONFIG_FW_LOADER=m
++# CONFIG_DEBUG_DRIVER is not set
++
++#
++# Memory Technology Devices (MTD)
++#
++CONFIG_MTD=y
++# CONFIG_MTD_DEBUG is not set
++CONFIG_MTD_CONCAT=y
++CONFIG_MTD_PARTITIONS=y
++# CONFIG_MTD_REDBOOT_PARTS is not set
++CONFIG_MTD_CMDLINE_PARTS=y
++# CONFIG_MTD_AFS_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++CONFIG_MTD_CHAR=y
++CONFIG_MTD_BLOCK=y
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_GEN_PROBE=y
++CONFIG_MTD_CFI_ADV_OPTIONS=y
++CONFIG_MTD_CFI_NOSWAP=y
++# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
++# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
++CONFIG_MTD_CFI_GEOMETRY=y
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++# CONFIG_MTD_CFI_I2 is not set
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++CONFIG_MTD_CFI_INTELEXT=y
++# CONFIG_MTD_CFI_AMDSTD is not set
++# CONFIG_MTD_CFI_STAA is not set
++CONFIG_MTD_CFI_UTIL=y
++CONFIG_MTD_RAM=y
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++# CONFIG_MTD_XIP is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_PHYSMAP is not set
++# CONFIG_MTD_ARM_INTEGRATOR is not set
++CONFIG_MTD_SA1100=y
++# CONFIG_MTD_EDB7312 is not set
++# CONFIG_MTD_IMPA7 is not set
++
++#
++# Self-contained MTD device drivers
++#
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLKMTD is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOC2000 is not set
++# CONFIG_MTD_DOC2001 is not set
++# CONFIG_MTD_DOC2001PLUS is not set
++
++#
++# NAND Flash Device Drivers
++#
++# CONFIG_MTD_NAND is not set
++
++#
++# Parallel port support
++#
++# CONFIG_PARPORT is not set
++
++#
++# Plug and Play support
++#
++# CONFIG_PNP is not set
++
++#
++# Block devices
++#
++# CONFIG_BLK_DEV_FD is not set
++# CONFIG_BLK_DEV_XD is not set
++# CONFIG_BLK_DEV_COW_COMMON is not set
++CONFIG_BLK_DEV_LOOP=m
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++# CONFIG_BLK_DEV_NBD is not set
++CONFIG_BLK_DEV_RAM=m
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=8192
++CONFIG_INITRAMFS_SOURCE=""
++# CONFIG_CDROM_PKTCDVD is not set
++
++#
++# IO Schedulers
++#
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_AS=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++# CONFIG_ATA_OVER_ETH is not set
++
++#
++# ATA/ATAPI/MFM/RLL support
++#
++# CONFIG_IDE is not set
++
++#
++# SCSI device support
++#
++# CONFIG_SCSI is not set
++
++#
++# Multi-device support (RAID and LVM)
++#
++# CONFIG_MD is not set
++
++#
++# Fusion MPT device support
++#
++
++#
++# IEEE 1394 (FireWire) support
++#
++
++#
++# I2O device support
++#
++
++#
++# Networking support
++#
++CONFIG_NET=y
++
++#
++# Networking options
++#
++CONFIG_PACKET=y
++CONFIG_PACKET_MMAP=y
++# CONFIG_NETLINK_DEV is not set
++CONFIG_UNIX=y
++# CONFIG_NET_KEY is not set
++CONFIG_INET=y
++# CONFIG_IP_MULTICAST is not set
++# CONFIG_IP_ADVANCED_ROUTER is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++# CONFIG_IP_PNP_RARP is not set
++# CONFIG_NET_IPIP is not set
++# CONFIG_NET_IPGRE is not set
++# CONFIG_ARPD is not set
++# CONFIG_SYN_COOKIES is not set
++# CONFIG_INET_AH is not set
++# CONFIG_INET_ESP is not set
++# CONFIG_INET_IPCOMP is not set
++# CONFIG_INET_TUNNEL is not set
++# CONFIG_IP_TCPDIAG is not set
++# CONFIG_IP_TCPDIAG_IPV6 is not set
++# CONFIG_IPV6 is not set
++# CONFIG_NETFILTER is not set
++
++#
++# SCTP Configuration (EXPERIMENTAL)
++#
++# CONFIG_IP_SCTP is not set
++# CONFIG_ATM is not set
++# CONFIG_BRIDGE is not set
++# CONFIG_VLAN_8021Q is not set
++# CONFIG_DECNET is not set
++# CONFIG_LLC2 is not set
++# CONFIG_IPX is not set
++# CONFIG_ATALK is not set
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_NET_DIVERT is not set
++# CONFIG_ECONET is not set
++# CONFIG_WAN_ROUTER is not set
++
++#
++# QoS and/or fair queueing
++#
++# CONFIG_NET_SCHED is not set
++# CONFIG_NET_CLS_ROUTE is not set
++
++#
++# Network testing
++#
++# CONFIG_NET_PKTGEN is not set
++# CONFIG_NETPOLL is not set
++# CONFIG_NET_POLL_CONTROLLER is not set
++# CONFIG_HAMRADIO is not set
++CONFIG_IRDA=m
++
++#
++# IrDA protocols
++#
++CONFIG_IRLAN=m
++CONFIG_IRNET=m
++CONFIG_IRCOMM=m
++# CONFIG_IRDA_ULTRA is not set
++
++#
++# IrDA options
++#
++# CONFIG_IRDA_CACHE_LAST_LSAP is not set
++# CONFIG_IRDA_FAST_RR is not set
++# CONFIG_IRDA_DEBUG is not set
++
++#
++# Infrared-port device drivers
++#
++
++#
++# SIR device drivers
++#
++CONFIG_IRTTY_SIR=m
++
++#
++# Dongle support
++#
++# CONFIG_DONGLE is not set
++
++#
++# Old SIR device drivers
++#
++CONFIG_IRPORT_SIR=m
++
++#
++# Old Serial dongle support
++#
++# CONFIG_DONGLE_OLD is not set
++
++#
++# FIR device drivers
++#
++# CONFIG_NSC_FIR is not set
++# CONFIG_WINBOND_FIR is not set
++# CONFIG_SMC_IRCC_FIR is not set
++# CONFIG_ALI_FIR is not set
++CONFIG_SA1100_FIR=m
++CONFIG_BT=m
++CONFIG_BT_L2CAP=m
++CONFIG_BT_SCO=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++# CONFIG_BT_HIDP is not set
++
++#
++# Bluetooth device drivers
++#
++# CONFIG_BT_HCIUART is not set
++# CONFIG_BT_HCIDTL1 is not set
++# CONFIG_BT_HCIBT3C is not set
++# CONFIG_BT_HCIBLUECARD is not set
++# CONFIG_BT_HCIBTUART is not set
++# CONFIG_BT_HCIVHCI is not set
++CONFIG_NETDEVICES=y
++CONFIG_DUMMY=y
++# CONFIG_BONDING is not set
++# CONFIG_EQUALIZER is not set
++# CONFIG_TUN is not set
++
++#
++# ARCnet devices
++#
++# CONFIG_ARCNET is not set
++
++#
++# Ethernet (10 or 100Mbit)
++#
++CONFIG_NET_ETHERNET=y
++CONFIG_MII=m
++# CONFIG_NET_VENDOR_3COM is not set
++# CONFIG_LANCE is not set
++# CONFIG_NET_VENDOR_SMC is not set
++# CONFIG_SMC91X is not set
++# CONFIG_NET_VENDOR_RACAL is not set
++# CONFIG_AT1700 is not set
++# CONFIG_DEPCA is not set
++# CONFIG_HP100 is not set
++# CONFIG_NET_ISA is not set
++CONFIG_NET_PCI=y
++# CONFIG_AC3200 is not set
++# CONFIG_APRICOT is not set
++# CONFIG_CS89x0 is not set
++# CONFIG_NET_POCKET is not set
++
++#
++# Ethernet (1000 Mbit)
++#
++
++#
++# Ethernet (10000 Mbit)
++#
++
++#
++# Token Ring devices
++#
++# CONFIG_TR is not set
++
++#
++# Wireless LAN (non-hamradio)
++#
++CONFIG_NET_RADIO=y
++
++#
++# Obsolete Wireless cards support (pre-802.11)
++#
++# CONFIG_STRIP is not set
++# CONFIG_ARLAN is not set
++# CONFIG_WAVELAN is not set
++CONFIG_PCMCIA_WAVELAN=m
++# CONFIG_PCMCIA_NETWAVE is not set
++
++#
++# Wireless 802.11 Frequency Hopping cards support
++#
++# CONFIG_PCMCIA_RAYCS is not set
++
++#
++# Wireless 802.11b ISA/PCI cards support
++#
++# CONFIG_HERMES is not set
++# CONFIG_ATMEL is not set
++
++#
++# Wireless 802.11b Pcmcia/Cardbus cards support
++#
++# CONFIG_AIRO_CS is not set
++# CONFIG_PCMCIA_WL3501 is not set
++CONFIG_NET_WIRELESS=y
++
++#
++# PCMCIA network device support
++#
++CONFIG_NET_PCMCIA=y
++CONFIG_PCMCIA_3C589=m
++CONFIG_PCMCIA_3C574=m
++# CONFIG_PCMCIA_FMVJ18X is not set
++CONFIG_PCMCIA_PCNET=m
++# CONFIG_PCMCIA_NMCLAN is not set
++CONFIG_PCMCIA_SMC91C92=m
++CONFIG_PCMCIA_XIRC2PS=m
++# CONFIG_PCMCIA_AXNET is not set
++
++#
++# Wan interfaces
++#
++# CONFIG_WAN is not set
++CONFIG_PPP=m
++CONFIG_PPP_MULTILINK=y
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_ASYNC=m
++CONFIG_PPP_SYNC_TTY=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPPOE=m
++# CONFIG_SLIP is not set
++# CONFIG_SHAPER is not set
++# CONFIG_NETCONSOLE is not set
++
++#
++# ISDN subsystem
++#
++# CONFIG_ISDN is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=800
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=600
++# CONFIG_INPUT_JOYDEV is not set
++CONFIG_INPUT_TSDEV=y
++CONFIG_INPUT_TSDEV_SCREEN_X=800
++CONFIG_INPUT_TSDEV_SCREEN_Y=600
++CONFIG_INPUT_EVDEV=m
++CONFIG_INPUT_EVBUG=y
++
++#
++# Input Device Drivers
++#
++# CONFIG_INPUT_KEYBOARD is not set
++# CONFIG_INPUT_MOUSE is not set
++# CONFIG_INPUT_JOYSTICK is not set
++# CONFIG_INPUT_TOUCHSCREEN is not set
++# CONFIG_INPUT_MISC is not set
++
++#
++# Hardware I/O ports
++#
++CONFIG_SERIO=m
++CONFIG_SERIO_SERPORT=m
++# CONFIG_SERIO_LIBPS2 is not set
++# CONFIG_SERIO_RAW is not set
++# CONFIG_GAMEPORT is not set
++CONFIG_SOUND_GAMEPORT=y
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++# CONFIG_SERIAL_NONSTANDARD is not set
++
++#
++# Serial drivers
++#
++# CONFIG_SERIAL_8250 is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_SA1100=y
++CONFIG_SERIAL_SA1100_CONSOLE=y
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++CONFIG_UNIX98_PTYS=y
++CONFIG_LEGACY_PTYS=y
++CONFIG_LEGACY_PTY_COUNT=256
++
++#
++# IPMI
++#
++# CONFIG_IPMI_HANDLER is not set
++
++#
++# Watchdog Cards
++#
++# CONFIG_WATCHDOG is not set
++# CONFIG_NVRAM is not set
++# CONFIG_RTC is not set
++# CONFIG_DTLK is not set
++# CONFIG_R3964 is not set
++
++#
++# Ftape, the floppy tape device driver
++#
++# CONFIG_DRM is not set
++
++#
++# PCMCIA character devices
++#
++# CONFIG_SYNCLINK_CS is not set
++# CONFIG_RAW_DRIVER is not set
++
++#
++# TPM devices
++#
++# CONFIG_TCG_TPM is not set
++
++#
++# I2C support
++#
++# CONFIG_I2C is not set
++
++#
++# Misc devices
++#
++
++#
++# Multimedia devices
++#
++# CONFIG_VIDEO_DEV is not set
++
++#
++# Digital Video Broadcasting Devices
++#
++# CONFIG_DVB is not set
++
++#
++# Graphics support
++#
++CONFIG_FB=y
++# CONFIG_FB_CFB_FILLRECT is not set
++# CONFIG_FB_CFB_COPYAREA is not set
++# CONFIG_FB_CFB_IMAGEBLIT is not set
++# CONFIG_FB_SOFT_CURSOR is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++# CONFIG_FB_SA1100 is not set
++# CONFIG_FB_VIRTUAL is not set
++
++#
++# Console display driver support
++#
++# CONFIG_VGA_CONSOLE is not set
++# CONFIG_MDA_CONSOLE is not set
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_FONTS is not set
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++
++#
++# Logo configuration
++#
++CONFIG_LOGO=y
++CONFIG_LOGO_LINUX_MONO=y
++CONFIG_LOGO_LINUX_VGA16=y
++CONFIG_LOGO_LINUX_CLUT224=y
++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++
++#
++# Sound
++#
++CONFIG_SOUND=y
++
++#
++# Advanced Linux Sound Architecture
++#
++# CONFIG_SND is not set
++
++#
++# Open Sound System
++#
++# CONFIG_SOUND_PRIME is not set
++
++#
++# USB support
++#
++CONFIG_USB_ARCH_HAS_HCD=y
++# CONFIG_USB_ARCH_HAS_OHCI is not set
++# CONFIG_USB is not set
++
++#
++# USB Gadget Support
++#
++# CONFIG_USB_GADGET is not set
++
++#
++# MMC/SD Card support
++#
++# CONFIG_MMC is not set
++
++#
++# File systems
++#
++CONFIG_EXT2_FS=m
++# CONFIG_EXT2_FS_XATTR is not set
++CONFIG_EXT3_FS=m
++CONFIG_EXT3_FS_XATTR=y
++# CONFIG_EXT3_FS_POSIX_ACL is not set
++# CONFIG_EXT3_FS_SECURITY is not set
++CONFIG_JBD=m
++# CONFIG_JBD_DEBUG is not set
++CONFIG_FS_MBCACHE=m
++CONFIG_REISERFS_FS=m
++# CONFIG_REISERFS_CHECK is not set
++CONFIG_REISERFS_PROC_INFO=y
++# CONFIG_REISERFS_FS_XATTR is not set
++# CONFIG_JFS_FS is not set
++
++#
++# XFS support
++#
++# CONFIG_XFS_FS is not set
++# CONFIG_MINIX_FS is not set
++# CONFIG_ROMFS_FS is not set
++# CONFIG_QUOTA is not set
++CONFIG_DNOTIFY=y
++# CONFIG_AUTOFS_FS is not set
++# CONFIG_AUTOFS4_FS is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++# CONFIG_ISO9660_FS is not set
++# CONFIG_UDF_FS is not set
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=m
++CONFIG_MSDOS_FS=m
++CONFIG_VFAT_FS=m
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_SYSFS=y
++CONFIG_DEVFS_FS=y
++CONFIG_DEVFS_MOUNT=y
++# CONFIG_DEVFS_DEBUG is not set
++# CONFIG_DEVPTS_FS_XATTR is not set
++# CONFIG_TMPFS is not set
++# CONFIG_HUGETLB_PAGE is not set
++CONFIG_RAMFS=y
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++# CONFIG_AFFS_FS is not set
++# CONFIG_HFS_FS is not set
++# CONFIG_HFSPLUS_FS is not set
++# CONFIG_BEFS_FS is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++CONFIG_JFFS_FS=m
++CONFIG_JFFS_FS_VERBOSE=0
++# CONFIG_JFFS_PROC_FS is not set
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_FS_DEBUG=0
++# CONFIG_JFFS2_FS_NAND is not set
++# CONFIG_JFFS2_FS_NOR_ECC is not set
++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
++CONFIG_JFFS2_ZLIB=y
++CONFIG_JFFS2_RTIME=y
++# CONFIG_JFFS2_RUBIN is not set
++CONFIG_CRAMFS=m
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_SYSV_FS is not set
++# CONFIG_UFS_FS is not set
++
++#
++# Network File Systems
++#
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++# CONFIG_ROOT_NFS is not set
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_SUNRPC=y
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++CONFIG_SMB_FS=m
++# CONFIG_SMB_NLS_DEFAULT is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
++
++#
++# Partition Types
++#
++# CONFIG_PARTITION_ADVANCED is not set
++CONFIG_MSDOS_PARTITION=y
++
++#
++# Native Language Support
++#
++CONFIG_NLS=y
++CONFIG_NLS_DEFAULT="iso8859-1"
++CONFIG_NLS_CODEPAGE_437=y
++# CONFIG_NLS_CODEPAGE_737 is not set
++# CONFIG_NLS_CODEPAGE_775 is not set
++CONFIG_NLS_CODEPAGE_850=y
++# CONFIG_NLS_CODEPAGE_852 is not set
++# CONFIG_NLS_CODEPAGE_855 is not set
++# CONFIG_NLS_CODEPAGE_857 is not set
++# CONFIG_NLS_CODEPAGE_860 is not set
++# CONFIG_NLS_CODEPAGE_861 is not set
++# CONFIG_NLS_CODEPAGE_862 is not set
++# CONFIG_NLS_CODEPAGE_863 is not set
++# CONFIG_NLS_CODEPAGE_864 is not set
++# CONFIG_NLS_CODEPAGE_865 is not set
++# CONFIG_NLS_CODEPAGE_866 is not set
++# CONFIG_NLS_CODEPAGE_869 is not set
++# CONFIG_NLS_CODEPAGE_936 is not set
++# CONFIG_NLS_CODEPAGE_950 is not set
++# CONFIG_NLS_CODEPAGE_932 is not set
++# CONFIG_NLS_CODEPAGE_949 is not set
++# CONFIG_NLS_CODEPAGE_874 is not set
++# CONFIG_NLS_ISO8859_8 is not set
++# CONFIG_NLS_CODEPAGE_1250 is not set
++# CONFIG_NLS_CODEPAGE_1251 is not set
++# CONFIG_NLS_ASCII is not set
++CONFIG_NLS_ISO8859_1=y
++# CONFIG_NLS_ISO8859_2 is not set
++# CONFIG_NLS_ISO8859_3 is not set
++# CONFIG_NLS_ISO8859_4 is not set
++# CONFIG_NLS_ISO8859_5 is not set
++# CONFIG_NLS_ISO8859_6 is not set
++# CONFIG_NLS_ISO8859_7 is not set
++# CONFIG_NLS_ISO8859_9 is not set
++# CONFIG_NLS_ISO8859_13 is not set
++# CONFIG_NLS_ISO8859_14 is not set
++CONFIG_NLS_ISO8859_15=y
++# CONFIG_NLS_KOI8_R is not set
++# CONFIG_NLS_KOI8_U is not set
++# CONFIG_NLS_UTF8 is not set
++
++#
++# Profiling support
++#
++# CONFIG_PROFILING is not set
++
++#
++# Kernel hacking
++#
++# CONFIG_PRINTK_TIME is not set
++CONFIG_DEBUG_KERNEL=y
++# CONFIG_MAGIC_SYSRQ is not set
++CONFIG_LOG_BUF_SHIFT=14
++# CONFIG_SCHEDSTATS is not set
++# CONFIG_DEBUG_SLAB is not set
++CONFIG_DEBUG_PREEMPT=y
++# CONFIG_DEBUG_SPINLOCK is not set
++# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
++# CONFIG_DEBUG_KOBJECT is not set
++CONFIG_DEBUG_BUGVERBOSE=y
++# CONFIG_DEBUG_INFO is not set
++# CONFIG_DEBUG_FS is not set
++CONFIG_FRAME_POINTER=y
++CONFIG_DEBUG_USER=y
++CONFIG_DEBUG_ERRORS=y
++CONFIG_DEBUG_LL=y
++# CONFIG_DEBUG_ICEDCC is not set
++
++#
++# Security options
++#
++# CONFIG_KEYS is not set
++# CONFIG_SECURITY is not set
++
++#
++# Cryptographic options
++#
++# CONFIG_CRYPTO is not set
++
++#
++# Hardware crypto devices
++#
++
++#
++# Library routines
++#
++CONFIG_CRC_CCITT=m
++CONFIG_CRC32=y
++# CONFIG_LIBCRC32C is not set
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=y
+diff -uNr linux-2.6.20.vanilla/drivers/video/Kconfig linux-2.6.20/drivers/video/Kconfig
+--- linux-2.6.20.vanilla/drivers/video/Kconfig 2007-02-10 19:02:14.000000000 +0100
++++ linux-2.6.20/drivers/video/Kconfig 2007-02-11 16:39:54.000000000 +0100
+@@ -1147,6 +1147,18 @@
+ help
+ If you have a S3 Trio say Y. Say N for S3 Virge.
+
++config FB_MQ200
++ bool "MQ200 Driver"
++ depends on (FB = y) && ARM && ARCH_SA1100
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is a MQ200 driver tested only on Simens SIMpads. You may need to
++ boot your SIMpad with a 2.4 SIMpad Kernel first in order to use this
++ driver. This is also needed if the SIMpad lost his power
++ connection (empty accu or accu disconnect).
++
+ config FB_SAVAGE
+ tristate "S3 Savage support"
+ depends on FB && PCI && EXPERIMENTAL
+diff -uNr linux-2.6.20.vanilla/drivers/video/Kconfig~ linux-2.6.20/drivers/video/Kconfig~
+--- linux-2.6.20.vanilla/drivers/video/Kconfig~ 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.20/drivers/video/Kconfig~ 2007-02-11 16:36:10.000000000 +0100
+@@ -0,0 +1,1662 @@
++#
++# Video configuration
++#
++
++menu "Graphics support"
++
++config FIRMWARE_EDID
++ bool "Enable firmware EDID"
++ default y
++ ---help---
++ This enables access to the EDID transferred from the firmware.
++ On the i386, this is from the Video BIOS. Enable this if DDC/I2C
++ transfers do not work for your driver and if you are using
++ nvidiafb, i810fb or savagefb.
++
++ In general, choosing Y for this option is safe. If you
++ experience extremely long delays while booting before you get
++ something on your display, try setting this to N. Matrox cards in
++ combination with certain motherboards and monitors are known to
++ suffer from this problem.
++
++config FB
++ tristate "Support for frame buffer devices"
++ ---help---
++ The frame buffer device provides an abstraction for the graphics
++ hardware. It represents the frame buffer of some video hardware and
++ allows application software to access the graphics hardware through
++ a well-defined interface, so the software doesn't need to know
++ anything about the low-level (hardware register) stuff.
++
++ Frame buffer devices work identically across the different
++ architectures supported by Linux and make the implementation of
++ application programs easier and more portable; at this point, an X
++ server exists which uses the frame buffer device exclusively.
++ On several non-X86 architectures, the frame buffer device is the
++ only way to use the graphics hardware.
++
++ The device is accessed through special device nodes, usually located
++ in the /dev directory, i.e. /dev/fb*.
++
++ You need an utility program called fbset to make full use of frame
++ buffer devices. Please read <file:Documentation/fb/framebuffer.txt>
++ and the Framebuffer-HOWTO at
++ <http://www.tahallah.demon.co.uk/programming/prog.html> for more
++ information.
++
++ Say Y here and to the driver for your graphics board below if you
++ are compiling a kernel for a non-x86 architecture.
++
++ If you are compiling for the x86 architecture, you can say Y if you
++ want to play with it, but it is not essential. Please note that
++ running graphical applications that directly touch the hardware
++ (e.g. an accelerated X server) and that are not frame buffer
++ device-aware may cause unexpected results. If unsure, say N.
++
++config FB_DDC
++ tristate
++ depends on FB && I2C && I2C_ALGOBIT
++ default n
++
++config FB_CFB_FILLRECT
++ tristate
++ depends on FB
++ default n
++ ---help---
++ Include the cfb_fillrect function for generic software rectangle
++ filling. This is used by drivers that don't provide their own
++ (accelerated) version.
++
++config FB_CFB_COPYAREA
++ tristate
++ depends on FB
++ default n
++ ---help---
++ Include the cfb_copyarea function for generic software area copying.
++ This is used by drivers that don't provide their own (accelerated)
++ version.
++
++config FB_CFB_IMAGEBLIT
++ tristate
++ depends on FB
++ default n
++ ---help---
++ Include the cfb_imageblit function for generic software image
++ blitting. This is used by drivers that don't provide their own
++ (accelerated) version.
++
++config FB_MACMODES
++ tristate
++ depends on FB
++ default n
++
++config FB_BACKLIGHT
++ bool
++ depends on FB
++ select BACKLIGHT_LCD_SUPPORT
++ select BACKLIGHT_CLASS_DEVICE
++ default n
++
++config FB_MODE_HELPERS
++ bool "Enable Video Mode Handling Helpers"
++ depends on FB
++ default n
++ ---help---
++ This enables functions for handling video modes using the
++ Generalized Timing Formula and the EDID parser. A few drivers rely
++ on this feature such as the radeonfb, rivafb, and the i810fb. If
++ your driver does not take advantage of this feature, choosing Y will
++ just increase the kernel size by about 5K.
++
++config FB_TILEBLITTING
++ bool "Enable Tile Blitting Support"
++ depends on FB
++ default n
++ ---help---
++ This enables tile blitting. Tile blitting is a drawing technique
++ where the screen is divided into rectangular sections (tiles), whereas
++ the standard blitting divides the screen into pixels. Because the
++ default drawing element is a tile, drawing functions will be passed
++ parameters in terms of number of tiles instead of number of pixels.
++ For example, to draw a single character, instead of using bitmaps,
++ an index to an array of bitmaps will be used. To clear or move a
++ rectangular section of a screen, the rectangle will be described in
++ terms of number of tiles in the x- and y-axis.
++
++ This is particularly important to one driver, matroxfb. If
++ unsure, say N.
++
++config FB_CIRRUS
++ tristate "Cirrus Logic support"
++ depends on FB && (ZORRO || PCI)
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ ---help---
++ This enables support for Cirrus Logic GD542x/543x based boards on
++ Amiga: SD64, Piccolo, Picasso II/II+, Picasso IV, or EGS Spectrum.
++
++ If you have a PCI-based system, this enables support for these
++ chips: GD-543x, GD-544x, GD-5480.
++
++ Please read the file <file:Documentation/fb/cirrusfb.txt>.
++
++ Say N unless you have such a graphics board or plan to get one
++ before you next recompile the kernel.
++
++config FB_PM2
++ tristate "Permedia2 support"
++ depends on FB && ((AMIGA && BROKEN) || PCI)
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the Permedia2 AGP frame
++ buffer card from ASK, aka `Graphic Blaster Exxtreme'. There is a
++ product page at
++ <http://www.ask.com.hk/product/Permedia%202/permedia2.htm>.
++
++config FB_PM2_FIFO_DISCONNECT
++ bool "enable FIFO disconnect feature"
++ depends on FB_PM2 && PCI
++ help
++ Support the Permedia2 FIFO disconnect feature (see CONFIG_FB_PM2).
++
++config FB_ARMCLCD
++ tristate "ARM PrimeCell PL110 support"
++ depends on FB && ARM && ARM_AMBA
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This framebuffer device driver is for the ARM PrimeCell PL110
++ Colour LCD controller. ARM PrimeCells provide the building
++ blocks for System on a Chip devices.
++
++ If you want to compile this as a module (=code which can be
++ inserted into and removed from the running kernel), say M
++ here and read <file:Documentation/modules.txt>. The module
++ will be called amba-clcd.
++
++choice
++
++ depends on FB_ARMCLCD && (ARCH_LH7A40X || ARCH_LH7952X)
++ prompt "LCD Panel"
++ default FB_ARMCLCD_SHARP_LQ035Q7DB02
++
++config FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT
++ bool "LogicPD LCD 3.5\" QVGA w/HRTFT IC"
++ help
++ This is an implementation of the Sharp LQ035Q7DB02, a 3.5"
++ color QVGA, HRTFT panel. The LogicPD device includes
++ an integrated HRTFT controller IC.
++ The native resolution is 240x320.
++
++config FB_ARMCLCD_SHARP_LQ057Q3DC02
++ bool "LogicPD LCD 5.7\" QVGA"
++ help
++ This is an implementation of the Sharp LQ057Q3DC02, a 5.7"
++ color QVGA, TFT panel. The LogicPD device includes an
++ The native resolution is 320x240.
++
++config FB_ARMCLCD_SHARP_LQ64D343
++ bool "LogicPD LCD 6.4\" VGA"
++ help
++ This is an implementation of the Sharp LQ64D343, a 6.4"
++ color VGA, TFT panel. The LogicPD device includes an
++ The native resolution is 640x480.
++
++config FB_ARMCLCD_SHARP_LQ10D368
++ bool "LogicPD LCD 10.4\" VGA"
++ help
++ This is an implementation of the Sharp LQ10D368, a 10.4"
++ color VGA, TFT panel. The LogicPD device includes an
++ The native resolution is 640x480.
++
++
++config FB_ARMCLCD_SHARP_LQ121S1DG41
++ bool "LogicPD LCD 12.1\" SVGA"
++ help
++ This is an implementation of the Sharp LQ121S1DG41, a 12.1"
++ color SVGA, TFT panel. The LogicPD device includes an
++ The native resolution is 800x600.
++
++ This panel requires a clock rate may be an integer fraction
++ of the base LCDCLK frequency. The driver will select the
++ highest frequency available that is lower than the maximum
++ allowed. The panel may flicker if the clock rate is
++ slower than the recommended minimum.
++
++config FB_ARMCLCD_AUO_A070VW01_WIDE
++ bool "AU Optronics A070VW01 LCD 7.0\" WIDE"
++ help
++ This is an implementation of the AU Optronics, a 7.0"
++ WIDE Color. The native resolution is 234x480.
++
++config FB_ARMCLCD_HITACHI
++ bool "Hitachi Wide Screen 800x480"
++ help
++ This is an implementation of the Hitachi 800x480.
++
++endchoice
++
++
++config FB_ACORN
++ bool "Acorn VIDC support"
++ depends on (FB = y) && ARM && (ARCH_ACORN || ARCH_CLPS7500)
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the Acorn VIDC graphics
++ hardware found in Acorn RISC PCs and other ARM-based machines. If
++ unsure, say N.
++
++config FB_CLPS711X
++ bool "CLPS711X LCD support"
++ depends on (FB = y) && ARM && ARCH_CLPS711X
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ Say Y to enable the Framebuffer driver for the CLPS7111 and
++ EP7212 processors.
++
++config FB_SA1100
++ bool "SA-1100 LCD support"
++ depends on (FB = y) && ARM && ARCH_SA1100
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is a framebuffer device for the SA-1100 LCD Controller.
++ See <http://www.linux-fbdev.org/> for information on framebuffer
++ devices.
++
++ If you plan to use the LCD display with your SA-1100 system, say
++ Y here.
++
++config FB_IMX
++ tristate "Motorola i.MX LCD support"
++ depends on FB && ARM && ARCH_IMX
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++
++config FB_CYBER2000
++ tristate "CyberPro 2000/2010/5000 support"
++ depends on FB && PCI && (BROKEN || !SPARC64)
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This enables support for the Integraphics CyberPro 20x0 and 5000
++ VGA chips used in the Rebel.com Netwinder and other machines.
++ Say Y if you have a NetWinder or a graphics card containing this
++ device, otherwise say N.
++
++config FB_APOLLO
++ bool
++ depends on (FB = y) && APOLLO
++ default y
++ select FB_CFB_FILLRECT
++ select FB_CFB_IMAGEBLIT
++
++config FB_Q40
++ bool
++ depends on (FB = y) && Q40
++ default y
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++
++config FB_AMIGA
++ tristate "Amiga native chipset support"
++ depends on FB && AMIGA
++ help
++ This is the frame buffer device driver for the builtin graphics
++ chipset found in Amigas.
++
++ To compile this driver as a module, choose M here: the
++ module will be called amifb.
++
++config FB_AMIGA_OCS
++ bool "Amiga OCS chipset support"
++ depends on FB_AMIGA
++ help
++ This enables support for the original Agnus and Denise video chips,
++ found in the Amiga 1000 and most A500's and A2000's. If you intend
++ to run Linux on any of these systems, say Y; otherwise say N.
++
++config FB_AMIGA_ECS
++ bool "Amiga ECS chipset support"
++ depends on FB_AMIGA
++ help
++ This enables support for the Enhanced Chip Set, found in later
++ A500's, later A2000's, the A600, the A3000, the A3000T and CDTV. If
++ you intend to run Linux on any of these systems, say Y; otherwise
++ say N.
++
++config FB_AMIGA_AGA
++ bool "Amiga AGA chipset support"
++ depends on FB_AMIGA
++ help
++ This enables support for the Advanced Graphics Architecture (also
++ known as the AGA or AA) Chip Set, found in the A1200, A4000, A4000T
++ and CD32. If you intend to run Linux on any of these systems, say Y;
++ otherwise say N.
++
++config FB_CYBER
++ tristate "Amiga CyberVision 64 support"
++ depends on FB && ZORRO && BROKEN
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This enables support for the Cybervision 64 graphics card from
++ Phase5. Please note that its use is not all that intuitive (i.e. if
++ you have any questions, be sure to ask!). Say N unless you have a
++ Cybervision 64 or plan to get one before you next recompile the
++ kernel. Please note that this driver DOES NOT support the
++ Cybervision 64/3D card, as they use incompatible video chips.
++
++config FB_VIRGE
++ bool "Amiga CyberVision 64/3D support "
++ depends on (FB = y) && ZORRO && BROKEN
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This enables support for the Cybervision 64/3D graphics card from
++ Phase5. Please note that its use is not all that intuitive (i.e. if
++ you have any questions, be sure to ask!). Say N unless you have a
++ Cybervision 64/3D or plan to get one before you next recompile the
++ kernel. Please note that this driver DOES NOT support the older
++ Cybervision 64 card, as they use incompatible video chips.
++
++config FB_RETINAZ3
++ tristate "Amiga Retina Z3 support"
++ depends on (FB = y) && ZORRO && BROKEN
++ help
++ This enables support for the Retina Z3 graphics card. Say N unless
++ you have a Retina Z3 or plan to get one before you next recompile
++ the kernel.
++
++config FB_FM2
++ bool "Amiga FrameMaster II/Rainbow II support"
++ depends on (FB = y) && ZORRO
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the Amiga FrameMaster
++ card from BSC (exhibited 1992 but not shipped as a CBM product).
++
++config FB_ARC
++ tristate "Arc Monochrome LCD board support"
++ depends on FB && X86
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This enables support for the Arc Monochrome LCD board. The board
++ is based on the KS-108 lcd controller and is typically a matrix
++ of 2*n chips. This driver was tested with a 128x64 panel. This
++ driver supports it for use with x86 SBCs through a 16 bit GPIO
++ interface (8 bit data, 8 bit control). If you anticipate using
++ this driver, say Y or M; otherwise say N. You must specify the
++ GPIO IO address to be used for setting control and data.
++
++config FB_ATARI
++ bool "Atari native chipset support"
++ depends on (FB = y) && ATARI && BROKEN
++ help
++ This is the frame buffer device driver for the builtin graphics
++ chipset found in Ataris.
++
++config FB_OF
++ bool "Open Firmware frame buffer device support"
++ depends on (FB = y) && (PPC64 || PPC_OF)
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select FB_MACMODES
++ help
++ Say Y if you want support with Open Firmware for your graphics
++ board.
++
++config FB_CONTROL
++ bool "Apple \"control\" display support"
++ depends on (FB = y) && PPC_PMAC && PPC32
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select FB_MACMODES
++ help
++ This driver supports a frame buffer for the graphics adapter in the
++ Power Macintosh 7300 and others.
++
++config FB_PLATINUM
++ bool "Apple \"platinum\" display support"
++ depends on (FB = y) && PPC_PMAC && PPC32
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select FB_MACMODES
++ help
++ This driver supports a frame buffer for the "platinum" graphics
++ adapter in some Power Macintoshes.
++
++config FB_VALKYRIE
++ bool "Apple \"valkyrie\" display support"
++ depends on (FB = y) && (MAC || (PPC_PMAC && PPC32))
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select FB_MACMODES
++ help
++ This driver supports a frame buffer for the "valkyrie" graphics
++ adapter in some Power Macintoshes.
++
++config FB_CT65550
++ bool "Chips 65550 display support"
++ depends on (FB = y) && PPC32
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the Chips & Technologies
++ 65550 graphics chip in PowerBooks.
++
++config FB_ASILIANT
++ bool "Asiliant (Chips) 69000 display support"
++ depends on (FB = y) && PCI
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the Asiliant 69030 chipset
++
++config FB_IMSTT
++ bool "IMS Twin Turbo display support"
++ depends on (FB = y) && PCI
++ select FB_CFB_IMAGEBLIT
++ select FB_MACMODES if PPC
++ help
++ The IMS Twin Turbo is a PCI-based frame buffer card bundled with
++ many Macintosh and compatible computers.
++
++config FB_VGA16
++ tristate "VGA 16-color graphics support"
++ depends on FB && (X86 || PPC)
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for VGA 16 color graphic
++ cards. Say Y if you have such a card.
++
++ To compile this driver as a module, choose M here: the
++ module will be called vga16fb.
++
++config FB_STI
++ tristate "HP STI frame buffer device support"
++ depends on FB && PARISC
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ default y
++ ---help---
++ STI refers to the HP "Standard Text Interface" which is a set of
++ BIOS routines contained in a ROM chip in HP PA-RISC based machines.
++ Enabling this option will implement the linux framebuffer device
++ using calls to the STI BIOS routines for initialisation.
++
++ If you enable this option, you will get a planar framebuffer device
++ /dev/fb which will work on the most common HP graphic cards of the
++ NGLE family, including the artist chips (in the 7xx and Bxxx series),
++ HCRX, HCRX24, CRX, CRX24 and VisEG series.
++
++ It is safe to enable this option, so you should probably say "Y".
++
++config FB_MAC
++ bool "Generic Macintosh display support"
++ depends on (FB = y) && MAC
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select FB_MACMODES
++
++# bool ' Apple DAFB display support' CONFIG_FB_DAFB
++config FB_HP300
++ bool
++ depends on (FB = y) && HP300
++ select FB_CFB_FILLRECT
++ select FB_CFB_IMAGEBLIT
++ default y
++
++config FB_TGA
++ tristate "TGA framebuffer support"
++ depends on FB && ALPHA
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select BITREVERSE
++ help
++ This is the frame buffer device driver for generic TGA graphic
++ cards. Say Y if you have one of those.
++
++config FB_VESA
++ bool "VESA VGA graphics support"
++ depends on (FB = y) && X86
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select VIDEO_SELECT
++ help
++ This is the frame buffer device driver for generic VESA 2.0
++ compliant graphic cards. The older VESA 1.2 cards are not supported.
++ You will get a boot time penguin logo at no additional cost. Please
++ read <file:Documentation/fb/vesafb.txt>. If unsure, say Y.
++
++config FB_IMAC
++ bool "Intel-based Macintosh Framebuffer Support"
++ depends on (FB = y) && X86 && EFI
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the Intel-based Macintosh
++
++config FB_HGA
++ tristate "Hercules mono graphics support"
++ depends on FB && X86
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ Say Y here if you have a Hercules mono graphics card.
++
++ To compile this driver as a module, choose M here: the
++ module will be called hgafb.
++
++ As this card technology is 15 years old, most people will answer N
++ here.
++
++config FB_HGA_ACCEL
++ bool "Hercules mono Acceleration functions (EXPERIMENTAL)"
++ depends on FB_HGA && EXPERIMENTAL
++ ---help---
++ This will compile the Hercules mono graphics with
++ acceleration functions.
++
++config FB_SGIVW
++ tristate "SGI Visual Workstation framebuffer support"
++ depends on FB && X86_VISWS
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ SGI Visual Workstation support for framebuffer graphics.
++
++config FB_GBE
++ bool "SGI Graphics Backend frame buffer support"
++ depends on (FB = y) && (SGI_IP32 || X86_VISWS)
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for SGI Graphics Backend.
++ This chip is used in SGI O2 and Visual Workstation 320/540.
++
++config FB_GBE_MEM
++ int "Video memory size in MB"
++ depends on FB_GBE
++ default 4
++ help
++ This is the amount of memory reserved for the framebuffer,
++ which can be any value between 1MB and 8MB.
++
++config FB_SUN3
++ bool "Sun3 framebuffer support"
++ depends on (FB = y) && (SUN3 || SUN3X) && BROKEN
++
++config FB_SBUS
++ bool "SBUS and UPA framebuffers"
++ depends on (FB = y) && SPARC
++ help
++ Say Y if you want support for SBUS or UPA based frame buffer device.
++
++config FB_BW2
++ bool "BWtwo support"
++ depends on (FB = y) && (SPARC && FB_SBUS || (SUN3 || SUN3X) && FB_SUN3)
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the BWtwo frame buffer.
++
++config FB_CG3
++ bool "CGthree support"
++ depends on (FB = y) && (SPARC && FB_SBUS || (SUN3 || SUN3X) && FB_SUN3)
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the CGthree frame buffer.
++
++config FB_CG6
++ bool "CGsix (GX,TurboGX) support"
++ depends on (FB = y) && (SPARC && FB_SBUS || (SUN3 || SUN3X) && FB_SUN3)
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the CGsix (GX, TurboGX)
++ frame buffer.
++
++config FB_PVR2
++ tristate "NEC PowerVR 2 display support"
++ depends on FB && SH_DREAMCAST
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ ---help---
++ Say Y here if you have a PowerVR 2 card in your box. If you plan to
++ run linux on your Dreamcast, you will have to say Y here.
++ This driver may or may not work on other PowerVR 2 cards, but is
++ totally untested. Use at your own risk. If unsure, say N.
++
++ To compile this driver as a module, choose M here: the
++ module will be called pvr2fb.
++
++ You can pass several parameters to the driver at boot time or at
++ module load time. The parameters look like "video=pvr2:XXX", where
++ the meaning of XXX can be found at the end of the main source file
++ (<file:drivers/video/pvr2fb.c>). Please see the file
++ <file:Documentation/fb/pvr2fb.txt>.
++
++config FB_EPSON1355
++ bool "Epson 1355 framebuffer support"
++ depends on (FB = y) && (SUPERH || ARCH_CEIVA)
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ Build in support for the SED1355 Epson Research Embedded RAMDAC
++ LCD/CRT Controller (since redesignated as the S1D13505) as a
++ framebuffer. Product specs at
++ <http://www.erd.epson.com/vdc/html/products.htm>.
++
++config FB_S1D13XXX
++ tristate "Epson S1D13XXX framebuffer support"
++ depends on FB
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ Support for S1D13XXX framebuffer device family (currently only
++ working with S1D13806). Product specs at
++ <http://www.erd.epson.com/vdc/html/legacy_13xxx.htm>
++
++config FB_NVIDIA
++ tristate "nVidia Framebuffer Support"
++ depends on FB && PCI
++ select I2C_ALGOBIT if FB_NVIDIA_I2C
++ select I2C if FB_NVIDIA_I2C
++ select FB_MODE_HELPERS
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select BITREVERSE
++ help
++ This driver supports graphics boards with the nVidia chips, TNT
++ and newer. For very old chipsets, such as the RIVA128, then use
++ the rivafb.
++ Say Y if you have such a graphics board.
++
++ To compile this driver as a module, choose M here: the
++ module will be called nvidiafb.
++
++config FB_NVIDIA_I2C
++ bool "Enable DDC Support"
++ depends on FB_NVIDIA
++ help
++ This enables I2C support for nVidia Chipsets. This is used
++ only for getting EDID information from the attached display
++ allowing for robust video mode handling and switching.
++
++ Because fbdev-2.6 requires that drivers must be able to
++ independently validate video mode parameters, you should say Y
++ here.
++
++config FB_NVIDIA_BACKLIGHT
++ bool "Support for backlight control"
++ depends on FB_NVIDIA && PMAC_BACKLIGHT
++ select FB_BACKLIGHT
++ default y
++ help
++ Say Y here if you want to control the backlight of your display.
++
++config FB_RIVA
++ tristate "nVidia Riva support"
++ depends on FB && PCI
++ select I2C_ALGOBIT if FB_RIVA_I2C
++ select I2C if FB_RIVA_I2C
++ select FB_DDC if FB_RIVA_I2C
++ select FB_MODE_HELPERS
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select BITREVERSE
++ help
++ This driver supports graphics boards with the nVidia Riva/Geforce
++ chips.
++ Say Y if you have such a graphics board.
++
++ To compile this driver as a module, choose M here: the
++ module will be called rivafb.
++
++config FB_RIVA_I2C
++ bool "Enable DDC Support"
++ depends on FB_RIVA
++ help
++ This enables I2C support for nVidia Chipsets. This is used
++ only for getting EDID information from the attached display
++ allowing for robust video mode handling and switching.
++
++ Because fbdev-2.6 requires that drivers must be able to
++ independently validate video mode parameters, you should say Y
++ here.
++
++config FB_RIVA_DEBUG
++ bool "Lots of debug output from Riva(nVidia) driver"
++ depends on FB_RIVA
++ default n
++ help
++ Say Y here if you want the Riva driver to output all sorts
++ of debugging information to provide to the maintainer when
++ something goes wrong.
++
++config FB_RIVA_BACKLIGHT
++ bool "Support for backlight control"
++ depends on FB_RIVA && PMAC_BACKLIGHT
++ select FB_BACKLIGHT
++ default y
++ help
++ Say Y here if you want to control the backlight of your display.
++
++config FB_I810
++ tristate "Intel 810/815 support (EXPERIMENTAL)"
++ depends on FB && EXPERIMENTAL && PCI && X86_32
++ select AGP
++ select AGP_INTEL
++ select FB_MODE_HELPERS
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This driver supports the on-board graphics built in to the Intel 810
++ and 815 chipsets. Say Y if you have and plan to use such a board.
++
++ To compile this driver as a module, choose M here: the
++ module will be called i810fb.
++
++ For more information, please read
++ <file:Documentation/fb/intel810.txt>
++
++config FB_I810_GTF
++ bool "use VESA Generalized Timing Formula"
++ depends on FB_I810
++ help
++ If you say Y, then the VESA standard, Generalized Timing Formula
++ or GTF, will be used to calculate the required video timing values
++ per video mode. Since the GTF allows nondiscrete timings
++ (nondiscrete being a range of values as opposed to discrete being a
++ set of values), you'll be able to use any combination of horizontal
++ and vertical resolutions, and vertical refresh rates without having
++ to specify your own timing parameters. This is especially useful
++ to maximize the performance of an aging display, or if you just
++ have a display with nonstandard dimensions. A VESA compliant
++ monitor is recommended, but can still work with non-compliant ones.
++ If you need or want this, then select this option. The timings may
++ not be compliant with Intel's recommended values. Use at your own
++ risk.
++
++ If you say N, the driver will revert to discrete video timings
++ using a set recommended by Intel in their documentation.
++
++ If unsure, say N.
++
++config FB_I810_I2C
++ bool "Enable DDC Support"
++ depends on FB_I810 && FB_I810_GTF
++ select I2C
++ select I2C_ALGOBIT
++ select FB_DDC
++ help
++
++config FB_INTEL
++ tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G support (EXPERIMENTAL)"
++ depends on FB && EXPERIMENTAL && PCI && X86
++ select AGP
++ select AGP_INTEL
++ select I2C_ALGOBIT if FB_INTEL_I2C
++ select I2C if FB_INTEL_I2C
++ select FB_MODE_HELPERS
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This driver supports the on-board graphics built in to the Intel
++ 830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM chipsets.
++ Say Y if you have and plan to use such a board.
++
++ If you say Y here and want DDC/I2C support you must first say Y to
++ "I2C support" and "I2C bit-banging support" in the character devices
++ section.
++
++ If you say M here then "I2C support" and "I2C bit-banging support"
++ can be build either as modules or built-in.
++
++ To compile this driver as a module, choose M here: the
++ module will be called intelfb.
++
++ For more information, please read <file:Documentation/fb/intelfb.txt>
++
++config FB_INTEL_DEBUG
++ bool "Intel driver Debug Messages"
++ depends on FB_INTEL
++ ---help---
++ Say Y here if you want the Intel driver to output all sorts
++ of debugging information to provide to the maintainer when
++ something goes wrong.
++
++config FB_INTEL_I2C
++ bool "DDC/I2C for Intel framebuffer support"
++ depends on FB_INTEL
++ default y
++ help
++ Say Y here if you want DDC/I2C support for your on-board Intel graphics.
++
++config FB_MATROX
++ tristate "Matrox acceleration"
++ depends on FB && PCI
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select FB_TILEBLITTING
++ select FB_MACMODES if PPC_PMAC
++ ---help---
++ Say Y here if you have a Matrox Millennium, Matrox Millennium II,
++ Matrox Mystique, Matrox Mystique 220, Matrox Productiva G100, Matrox
++ Mystique G200, Matrox Millennium G200, Matrox Marvel G200 video,
++ Matrox G400, G450 or G550 card in your box.
++
++ To compile this driver as a module, choose M here: the
++ module will be called matroxfb.
++
++ You can pass several parameters to the driver at boot time or at
++ module load time. The parameters look like "video=matrox:XXX", and
++ are described in <file:Documentation/fb/matroxfb.txt>.
++
++config FB_MATROX_MILLENIUM
++ bool "Millennium I/II support"
++ depends on FB_MATROX
++ help
++ Say Y here if you have a Matrox Millennium or Matrox Millennium II
++ video card. If you select "Advanced lowlevel driver options" below,
++ you should check 4 bpp packed pixel, 8 bpp packed pixel, 16 bpp
++ packed pixel, 24 bpp packed pixel and 32 bpp packed pixel. You can
++ also use font widths different from 8.
++
++config FB_MATROX_MYSTIQUE
++ bool "Mystique support"
++ depends on FB_MATROX
++ help
++ Say Y here if you have a Matrox Mystique or Matrox Mystique 220
++ video card. If you select "Advanced lowlevel driver options" below,
++ you should check 8 bpp packed pixel, 16 bpp packed pixel, 24 bpp
++ packed pixel and 32 bpp packed pixel. You can also use font widths
++ different from 8.
++
++config FB_MATROX_G
++ bool "G100/G200/G400/G450/G550 support"
++ depends on FB_MATROX
++ ---help---
++ Say Y here if you have a Matrox G100, G200, G400, G450 or G550 based
++ video card. If you select "Advanced lowlevel driver options", you
++ should check 8 bpp packed pixel, 16 bpp packed pixel, 24 bpp packed
++ pixel and 32 bpp packed pixel. You can also use font widths
++ different from 8.
++
++ If you need support for G400 secondary head, you must first say Y to
++ "I2C support" in the character devices section, and then to
++ "Matrox I2C support" and "G400 second head support" here in the
++ framebuffer section. G450/G550 secondary head and digital output
++ are supported without additional modules.
++
++ The driver starts in monitor mode. You must use the matroxset tool
++ (available at <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to
++ swap primary and secondary head outputs, or to change output mode.
++ Secondary head driver always start in 640x480 resolution and you
++ must use fbset to change it.
++
++ Do not forget that second head supports only 16 and 32 bpp
++ packed pixels, so it is a good idea to compile them into the kernel
++ too. You can use only some font widths, as the driver uses generic
++ painting procedures (the secondary head does not use acceleration
++ engine).
++
++ G450/G550 hardware can display TV picture only from secondary CRTC,
++ and it performs no scaling, so picture must have 525 or 625 lines.
++
++config FB_MATROX_I2C
++ tristate "Matrox I2C support"
++ depends on FB_MATROX && I2C
++ select I2C_ALGOBIT
++ ---help---
++ This drivers creates I2C buses which are needed for accessing the
++ DDC (I2C) bus present on all Matroxes, an I2C bus which
++ interconnects Matrox optional devices, like MGA-TVO on G200 and
++ G400, and the secondary head DDC bus, present on G400 only.
++
++ You can say Y or M here if you want to experiment with monitor
++ detection code. You must say Y or M here if you want to use either
++ second head of G400 or MGA-TVO on G200 or G400.
++
++ If you compile it as module, it will create a module named
++ i2c-matroxfb.
++
++config FB_MATROX_MAVEN
++ tristate "G400 second head support"
++ depends on FB_MATROX_G && FB_MATROX_I2C
++ ---help---
++ WARNING !!! This support does not work with G450 !!!
++
++ Say Y or M here if you want to use a secondary head (meaning two
++ monitors in parallel) on G400 or MGA-TVO add-on on G200. Secondary
++ head is not compatible with accelerated XFree 3.3.x SVGA servers -
++ secondary head output is blanked while you are in X. With XFree
++ 3.9.17 preview you can use both heads if you use SVGA over fbdev or
++ the fbdev driver on first head and the fbdev driver on second head.
++
++ If you compile it as module, two modules are created,
++ matroxfb_crtc2 and matroxfb_maven. Matroxfb_maven is needed for
++ both G200 and G400, matroxfb_crtc2 is needed only by G400. You must
++ also load i2c-matroxfb to get it to run.
++
++ The driver starts in monitor mode and you must use the matroxset
++ tool (available at
++ <ftp://platan.vc.cvut.cz/pub/linux/matrox-latest/>) to switch it to
++ PAL or NTSC or to swap primary and secondary head outputs.
++ Secondary head driver also always start in 640x480 resolution, you
++ must use fbset to change it.
++
++ Also do not forget that second head supports only 16 and 32 bpp
++ packed pixels, so it is a good idea to compile them into the kernel
++ too. You can use only some font widths, as the driver uses generic
++ painting procedures (the secondary head does not use acceleration
++ engine).
++
++config FB_MATROX_MULTIHEAD
++ bool "Multihead support"
++ depends on FB_MATROX
++ ---help---
++ Say Y here if you have more than one (supported) Matrox device in
++ your computer and you want to use all of them for different monitors
++ ("multihead"). If you have only one device, you should say N because
++ the driver compiled with Y is larger and a bit slower, especially on
++ ia32 (ix86).
++
++ If you said M to "Matrox unified accelerated driver" and N here, you
++ will still be able to use several Matrox devices simultaneously:
++ insert several instances of the module matroxfb into the kernel
++ with insmod, supplying the parameter "dev=N" where N is 0, 1, etc.
++ for the different Matrox devices. This method is slightly faster but
++ uses 40 KB of kernel memory per Matrox card.
++
++ There is no need for enabling 'Matrox multihead support' if you have
++ only one Matrox card in the box.
++
++config FB_RADEON
++ tristate "ATI Radeon display support"
++ depends on FB && PCI
++ select I2C_ALGOBIT if FB_RADEON_I2C
++ select I2C if FB_RADEON_I2C
++ select FB_DDC if FB_RADEON_I2C
++ select FB_MODE_HELPERS
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select FB_MACMODES if PPC_OF
++ help
++ Choose this option if you want to use an ATI Radeon graphics card as
++ a framebuffer device. There are both PCI and AGP versions. You
++ don't need to choose this to run the Radeon in plain VGA mode.
++
++ If you say Y here and want DDC/I2C support you must first say Y to
++ "I2C support" and "I2C bit-banging support" in the character devices
++ section.
++
++ If you say M here then "I2C support" and "I2C bit-banging support"
++ can be build either as modules or built-in.
++
++ There is a product page at
++ http://apps.ati.com/ATIcompare/
++
++config FB_RADEON_I2C
++ bool "DDC/I2C for ATI Radeon support"
++ depends on FB_RADEON
++ default y
++ help
++ Say Y here if you want DDC/I2C support for your Radeon board.
++
++config FB_RADEON_BACKLIGHT
++ bool "Support for backlight control"
++ depends on FB_RADEON && PMAC_BACKLIGHT
++ select FB_BACKLIGHT
++ default y
++ help
++ Say Y here if you want to control the backlight of your display.
++
++config FB_RADEON_DEBUG
++ bool "Lots of debug output from Radeon driver"
++ depends on FB_RADEON
++ default n
++ help
++ Say Y here if you want the Radeon driver to output all sorts
++ of debugging information to provide to the maintainer when
++ something goes wrong.
++
++config FB_ATY128
++ tristate "ATI Rage128 display support"
++ depends on FB && PCI
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select FB_MACMODES if PPC_PMAC
++ help
++ This driver supports graphics boards with the ATI Rage128 chips.
++ Say Y if you have such a graphics board and read
++ <file:Documentation/fb/aty128fb.txt>.
++
++ To compile this driver as a module, choose M here: the
++ module will be called aty128fb.
++
++config FB_ATY128_BACKLIGHT
++ bool "Support for backlight control"
++ depends on FB_ATY128 && PMAC_BACKLIGHT
++ select FB_BACKLIGHT
++ default y
++ help
++ Say Y here if you want to control the backlight of your display.
++
++config FB_ATY
++ tristate "ATI Mach64 display support" if PCI || ATARI
++ depends on FB && !SPARC32
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select FB_MACMODES if PPC
++ help
++ This driver supports graphics boards with the ATI Mach64 chips.
++ Say Y if you have such a graphics board.
++
++ To compile this driver as a module, choose M here: the
++ module will be called atyfb.
++
++config FB_ATY_CT
++ bool "Mach64 CT/VT/GT/LT (incl. 3D RAGE) support"
++ depends on PCI && FB_ATY
++ default y if SPARC64 && FB_PCI
++ help
++ Say Y here to support use of ATI's 64-bit Rage boards (or other
++ boards based on the Mach64 CT, VT, GT, and LT chipsets) as a
++ framebuffer device. The ATI product support page for these boards
++ is at <http://support.ati.com/products/pc/mach64/>.
++
++config FB_ATY_GENERIC_LCD
++ bool "Mach64 generic LCD support (EXPERIMENTAL)"
++ depends on FB_ATY_CT
++ help
++ Say Y if you have a laptop with an ATI Rage LT PRO, Rage Mobility,
++ Rage XC, or Rage XL chipset.
++
++config FB_ATY_GX
++ bool "Mach64 GX support" if PCI
++ depends on FB_ATY
++ default y if ATARI
++ help
++ Say Y here to support use of the ATI Mach64 Graphics Expression
++ board (or other boards based on the Mach64 GX chipset) as a
++ framebuffer device. The ATI product support page for these boards
++ is at
++ <http://support.ati.com/products/pc/mach64/graphics_xpression.html>.
++
++config FB_ATY_BACKLIGHT
++ bool "Support for backlight control"
++ depends on FB_ATY && PMAC_BACKLIGHT
++ select FB_BACKLIGHT
++ default y
++ help
++ Say Y here if you want to control the backlight of your display.
++
++config FB_S3TRIO
++ bool "S3 Trio display support"
++ depends on (FB = y) && PPC && BROKEN
++ help
++ If you have a S3 Trio say Y. Say N for S3 Virge.
++
++config FB_SAVAGE
++ tristate "S3 Savage support"
++ depends on FB && PCI && EXPERIMENTAL
++ select I2C_ALGOBIT if FB_SAVAGE_I2C
++ select I2C if FB_SAVAGE_I2C
++ select FB_DDC if FB_SAVAGE_I2C
++ select FB_MODE_HELPERS
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This driver supports notebooks and computers with S3 Savage PCI/AGP
++ chips.
++
++ Say Y if you have such a graphics card.
++
++ To compile this driver as a module, choose M here; the module
++ will be called savagefb.
++
++config FB_SAVAGE_I2C
++ bool "Enable DDC2 Support"
++ depends on FB_SAVAGE
++ help
++ This enables I2C support for S3 Savage Chipsets. This is used
++ only for getting EDID information from the attached display
++ allowing for robust video mode handling and switching.
++
++ Because fbdev-2.6 requires that drivers must be able to
++ independently validate video mode parameters, you should say Y
++ here.
++
++config FB_SAVAGE_ACCEL
++ bool "Enable Console Acceleration"
++ depends on FB_SAVAGE
++ default n
++ help
++ This option will compile in console acceleration support. If
++ the resulting framebuffer console has bothersome glitches, then
++ choose N here.
++
++config FB_SIS
++ tristate "SiS/XGI display support"
++ depends on FB && PCI
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the SiS 300, 315, 330
++ and 340 series as well as XGI V3XT, V5, V8, Z7 graphics chipsets.
++ Specs available at <http://www.sis.com> and <http://www.xgitech.com>.
++
++ To compile this driver as a module, choose M here; the module
++ will be called sisfb.
++
++config FB_SIS_300
++ bool "SiS 300 series support"
++ depends on FB_SIS
++ help
++ Say Y here to support use of the SiS 300/305, 540, 630 and 730.
++
++config FB_SIS_315
++ bool "SiS 315/330/340 series and XGI support"
++ depends on FB_SIS
++ help
++ Say Y here to support use of the SiS 315, 330 and 340 series
++ (315/H/PRO, 55x, 650, 651, 740, 330, 661, 741, 760, 761) as well
++ as XGI V3XT, V5, V8 and Z7.
++
++config FB_NEOMAGIC
++ tristate "NeoMagic display support"
++ depends on FB && PCI
++ select FB_MODE_HELPERS
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This driver supports notebooks with NeoMagic PCI chips.
++ Say Y if you have such a graphics card.
++
++ To compile this driver as a module, choose M here: the
++ module will be called neofb.
++
++config FB_KYRO
++ tristate "IMG Kyro support"
++ depends on FB && PCI
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ Say Y here if you have a STG4000 / Kyro / PowerVR 3 based
++ graphics board.
++
++ To compile this driver as a module, choose M here: the
++ module will be called kyrofb.
++
++config FB_3DFX
++ tristate "3Dfx Banshee/Voodoo3 display support"
++ depends on FB && PCI
++ select FB_CFB_IMAGEBLIT
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ help
++ This driver supports graphics boards with the 3Dfx Banshee/Voodoo3
++ chips. Say Y if you have such a graphics board.
++
++ To compile this driver as a module, choose M here: the
++ module will be called tdfxfb.
++
++config FB_3DFX_ACCEL
++ bool "3Dfx Banshee/Voodoo3 Acceleration functions (EXPERIMENTAL)"
++ depends on FB_3DFX && EXPERIMENTAL
++ ---help---
++ This will compile the 3Dfx Banshee/Voodoo3 frame buffer device
++ with acceleration functions.
++
++
++config FB_VOODOO1
++ tristate "3Dfx Voodoo Graphics (sst1) support"
++ depends on FB && PCI
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ ---help---
++ Say Y here if you have a 3Dfx Voodoo Graphics (Voodoo1/sst1) or
++ Voodoo2 (cvg) based graphics card.
++
++ To compile this driver as a module, choose M here: the
++ module will be called sstfb.
++
++ WARNING: Do not use any application that uses the 3D engine
++ (namely glide) while using this driver.
++ Please read the <file:Documentation/fb/README-sstfb.txt> for supported
++ options and other important info support.
++
++config FB_CYBLA
++ tristate "Cyberblade/i1 support"
++ depends on FB && PCI && X86_32 && !64BIT
++ select FB_CFB_IMAGEBLIT
++ select VIDEO_SELECT
++ ---help---
++ This driver is supposed to support the Trident Cyberblade/i1
++ graphics core integrated in the VIA VT8601A North Bridge,
++ also known as VIA Apollo PLE133.
++
++ Status:
++ - Developed, tested and working on EPIA 5000 and EPIA 800.
++ - Does work reliable on all systems with CRT/LCD connected to
++ normal VGA ports.
++ - Should work on systems that do use the internal LCD port, but
++ this is absolutely not tested.
++
++ Character imageblit, copyarea and rectangle fill are hw accelerated,
++ ypan scrolling is used by default.
++
++ Please do read <file:Documentation/fb/cyblafb/*>.
++
++ To compile this driver as a module, choose M here: the
++ module will be called cyblafb.
++
++config FB_TRIDENT
++ tristate "Trident support"
++ depends on FB && PCI
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ ---help---
++ This driver is supposed to support graphics boards with the
++ Trident CyberXXXX/Image/CyberBlade chips mostly found in laptops
++ but also on some motherboards. For more information, read
++ <file:Documentation/fb/tridentfb.txt>
++
++ Cyberblade/i1 support will be removed soon, use the cyblafb driver
++ instead.
++
++ Say Y if you have such a graphics board.
++
++
++ To compile this driver as a module, choose M here: the
++ module will be called tridentfb.
++
++config FB_TRIDENT_ACCEL
++ bool "Trident Acceleration functions (EXPERIMENTAL)"
++ depends on FB_TRIDENT && EXPERIMENTAL
++ ---help---
++ This will compile the Trident frame buffer device with
++ acceleration functions.
++
++config FB_PM3
++ tristate "Permedia3 support"
++ depends on FB && PCI && BROKEN
++ help
++ This is the frame buffer device driver for the 3DLabs Permedia3
++ chipset, used in Formac ProFormance III, 3DLabs Oxygen VX1 &
++ similar boards, 3DLabs Permedia3 Create!, Appian Jeronimo 2000
++ and maybe other boards.
++
++config FB_AU1100
++ bool "Au1100 LCD Driver"
++ depends on (FB = y) && EXPERIMENTAL && PCI && MIPS && MIPS_PB1100=y
++
++config FB_AU1200
++ bool "Au1200 LCD Driver"
++ depends on FB && MIPS && SOC_AU1200
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the framebuffer driver for the AMD Au1200 SOC. It can drive
++ various panels and CRTs by passing in kernel cmd line option
++ au1200fb:panel=<name>.
++
++source "drivers/video/geode/Kconfig"
++
++config FB_FFB
++ bool "Creator/Creator3D/Elite3D support"
++ depends on FB_SBUS && SPARC64
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the Creator, Creator3D,
++ and Elite3D graphics boards.
++
++config FB_TCX
++ bool "TCX (SS4/SS5 only) support"
++ depends on FB_SBUS
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the TCX 24/8bit frame
++ buffer.
++
++config FB_CG14
++ bool "CGfourteen (SX) support"
++ depends on FB_SBUS
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the CGfourteen frame
++ buffer on Desktop SPARCsystems with the SX graphics option.
++
++config FB_P9100
++ bool "P9100 (Sparcbook 3 only) support"
++ depends on FB_SBUS
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the P9100 card
++ supported on Sparcbook 3 machines.
++
++config FB_LEO
++ bool "Leo (ZX) support"
++ depends on FB_SBUS
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the SBUS-based Sun ZX
++ (leo) frame buffer cards.
++
++config FB_PCI
++ bool "PCI framebuffers"
++ depends on (FB = y) && PCI && SPARC
++
++config FB_IGA
++ bool "IGA 168x display support"
++ depends on SPARC32 && FB_PCI
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the framebuffer device for the INTERGRAPHICS 1680 and
++ successor frame buffer cards.
++
++config FB_HIT
++ tristate "HD64461 Frame Buffer support"
++ depends on FB && HD64461
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This is the frame buffer device driver for the Hitachi HD64461 LCD
++ frame buffer card.
++
++config FB_PMAG_AA
++ bool "PMAG-AA TURBOchannel framebuffer support"
++ depends on (FB = y) && TC
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ Support for the PMAG-AA TURBOchannel framebuffer card (1280x1024x1)
++ used mainly in the MIPS-based DECstation series.
++
++config FB_PMAG_BA
++ bool "PMAG-BA TURBOchannel framebuffer support"
++ depends on (FB = y) && TC
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ Support for the PMAG-BA TURBOchannel framebuffer card (1024x864x8)
++ used mainly in the MIPS-based DECstation series.
++
++config FB_PMAGB_B
++ bool "PMAGB-B TURBOchannel framebuffer support"
++ depends on (FB = y) && TC
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ Support for the PMAGB-B TURBOchannel framebuffer card used mainly
++ in the MIPS-based DECstation series. The card is currently only
++ supported in 1280x1024x8 mode.
++
++config FB_MAXINE
++ bool "Maxine (Personal DECstation) onboard framebuffer support"
++ depends on (FB = y) && MACH_DECSTATION
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ Support for the onboard framebuffer (1024x768x8) in the Personal
++ DECstation series (Personal DECstation 5000/20, /25, /33, /50,
++ Codename "Maxine").
++
++config FB_TX3912
++ bool "TMPTX3912/PR31700 frame buffer support"
++ depends on (FB = y) && NINO
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ The TX3912 is a Toshiba RISC processor based on the MIPS 3900 core
++ see <http://www.toshiba.com/taec/components/Generic/risc/tx3912.htm>.
++
++ Say Y here to enable kernel support for the on-board framebuffer.
++
++config FB_G364
++ bool "G364 frame buffer support"
++ depends on (FB = y) && (MIPS_MAGNUM_4000 || OLIVETTI_M700)
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ The G364 driver is the framebuffer used in MIPS Magnum 4000 and
++ Olivetti M700-10 systems.
++
++config FB_68328
++ bool "Motorola 68328 native frame buffer support"
++ depends on FB && (M68328 || M68EZ328 || M68VZ328)
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ Say Y here if you want to support the built-in frame buffer of
++ the Motorola 68328 CPU family.
++
++config FB_PXA
++ tristate "PXA LCD framebuffer support"
++ depends on FB && ARCH_PXA
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ ---help---
++ Frame buffer driver for the built-in LCD controller in the Intel
++ PXA2x0 processor.
++
++ This driver is also available as a module ( = code which can be
++ inserted and removed from the running kernel whenever you want). The
++ module will be called pxafb. If you want to compile it as a module,
++ say M here and read <file:Documentation/modules.txt>.
++
++ If unsure, say N.
++
++config FB_PXA_PARAMETERS
++ bool "PXA LCD command line parameters"
++ default n
++ depends on FB_PXA
++ ---help---
++ Enable the use of kernel command line or module parameters
++ to configure the physical properties of the LCD panel when
++ using the PXA LCD driver.
++
++ This option allows you to override the panel parameters
++ supplied by the platform in order to support multiple
++ different models of flatpanel. If you will only be using a
++ single model of flatpanel then you can safely leave this
++ option disabled.
++
++ <file:Documentation/fb/pxafb.txt> describes the available parameters.
++
++config FB_MBX
++ tristate "2700G LCD framebuffer support"
++ depends on FB && ARCH_PXA
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ ---help---
++ Framebuffer driver for the Intel 2700G (Marathon) Graphics
++ Accelerator
++
++config FB_MBX_DEBUG
++ bool "Enable debugging info via debugfs"
++ depends on FB_MBX && DEBUG_FS
++ default n
++ ---help---
++ Enable this if you want debugging information using the debug
++ filesystem (debugfs)
++
++ If unsure, say N.
++
++config FB_W100
++ tristate "W100 frame buffer support"
++ depends on FB && PXA_SHARPSL
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ ---help---
++ Frame buffer driver for the w100 as found on the Sharp SL-Cxx series.
++
++ This driver is also available as a module ( = code which can be
++ inserted and removed from the running kernel whenever you want). The
++ module will be called w100fb. If you want to compile it as a module,
++ say M here and read <file:Documentation/modules.txt>.
++
++ If unsure, say N.
++
++config FB_S3C2410
++ tristate "S3C2410 LCD framebuffer support"
++ depends on FB && ARCH_S3C2410
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ ---help---
++ Frame buffer driver for the built-in LCD controller in the Samsung
++ S3C2410 processor.
++
++ This driver is also available as a module ( = code which can be
++ inserted and removed from the running kernel whenever you want). The
++ module will be called s3c2410fb. If you want to compile it as a module,
++ say M here and read <file:Documentation/modules.txt>.
++
++ If unsure, say N.
++config FB_S3C2410_DEBUG
++ bool "S3C2410 lcd debug messages"
++ depends on FB_S3C2410
++ help
++ Turn on debugging messages. Note that you can set/unset at run time
++ through sysfs
++
++config FB_PNX4008_DUM
++ tristate "Display Update Module support on Philips PNX4008 board"
++ depends on FB && ARCH_PNX4008
++ ---help---
++ Say Y here to enable support for PNX4008 Display Update Module (DUM)
++
++config FB_PNX4008_DUM_RGB
++ tristate "RGB Framebuffer support on Philips PNX4008 board"
++ depends on FB_PNX4008_DUM
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ ---help---
++ Say Y here to enable support for PNX4008 RGB Framebuffer
++
++config FB_IBM_GXT4500
++ tristate "Framebuffer support for IBM GXT4500P adaptor"
++ depends on PPC
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ ---help---
++ Say Y here to enable support for the IBM GXT4500P display
++ adaptor, found on some IBM System P (pSeries) machines.
++
++config FB_VIRTUAL
++ tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
++ depends on FB
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ ---help---
++ This is a `virtual' frame buffer device. It operates on a chunk of
++ unswappable kernel memory instead of on the memory of a graphics
++ board. This means you cannot see any output sent to this frame
++ buffer device, while it does consume precious memory. The main use
++ of this frame buffer device is testing and debugging the frame
++ buffer subsystem. Do NOT enable it for normal systems! To protect
++ the innocent, it has to be enabled explicitly at boot time using the
++ kernel option `video=vfb:'.
++
++ To compile this driver as a module, choose M here: the
++ module will be called vfb. In order to load it, you must use
++ the vfb_enable=1 option.
++
++ If unsure, say N.
++if VT
++ source "drivers/video/console/Kconfig"
++endif
++
++if FB || SGI_NEWPORT_CONSOLE
++ source "drivers/video/logo/Kconfig"
++endif
++
++if SYSFS
++ source "drivers/video/backlight/Kconfig"
++endif
++
++endmenu
++
+diff -uNr linux-2.6.20.vanilla/drivers/video/Makefile linux-2.6.20/drivers/video/Makefile
+--- linux-2.6.20.vanilla/drivers/video/Makefile 2007-02-10 19:02:14.000000000 +0100
++++ linux-2.6.20/drivers/video/Makefile 2007-02-11 16:40:07.000000000 +0100
+@@ -30,6 +30,7 @@
+ obj-$(CONFIG_FB_PM2) += pm2fb.o
+ obj-$(CONFIG_FB_PM3) += pm3fb.o
+
++obj-$(CONFIG_FB_MQ200) += mq200/
+ obj-$(CONFIG_FB_MATROX) += matrox/
+ obj-$(CONFIG_FB_RIVA) += riva/ vgastate.o
+ obj-$(CONFIG_FB_NVIDIA) += nvidia/
+diff -uNr linux-2.6.20.vanilla/drivers/video/mq200/Makefile linux-2.6.20/drivers/video/mq200/Makefile
+--- linux-2.6.20.vanilla/drivers/video/mq200/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.20/drivers/video/mq200/Makefile 2007-02-11 16:41:44.000000000 +0100
+@@ -0,0 +1,6 @@
++# Makefile for mq200 video driver
++# 4 Aug 2003, Holger Hans Peter Freyther
++# 2 Jan 2007, mr nice
++
++obj-$(CONFIG_FB_MQ200) += mq_skeleton.o mq_external.o
++
+diff -uNr linux-2.6.20.vanilla/drivers/video/mq200/mq200_data.h linux-2.6.20/drivers/video/mq200/mq200_data.h
+--- linux-2.6.20.vanilla/drivers/video/mq200/mq200_data.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.20/drivers/video/mq200/mq200_data.h 2007-02-11 16:41:09.000000000 +0100
+@@ -0,0 +1,893 @@
++/*
++ * From ucLinux mq200fb.c and mq200fb.h
++ */
++
++#ifndef __MQ200_FB_H__
++#define __MQ200_FB_H__
++
++struct mq200_io_regions {
++ u32 fb_size; /* framebuffer size */
++ unsigned long phys_mmio_base; /* physical register memory base */
++ unsigned long virt_mmio_base; /* virtual start of registers */
++ unsigned long phys_fb_base; /* physical address of frame buffer */
++ unsigned long virt_fb_base; /* virtual start of the framebuffer */
++};
++
++#define MQ200_MONITOR_HORI_RES(info) info->monitor_info.horizontal_res
++#define MQ200_MONITOR_VERT_RES(info) info->monitor_info.vertical_res
++#define MQ200_MONITOR_DEPTH(info) info->monitor_info.depth
++#define MQ200_MONITOR_LINE_LENGTH(info) info->monitor_info.line_length
++
++struct mq200_monitor_info {
++ unsigned int horizontal_res;
++ unsigned int vertical_res;
++ unsigned int depth;
++ unsigned int refresh;
++ unsigned int line_length;
++ unsigned long flags;
++};
++
++
++/**
++ * Addresses of Module
++ */
++#define MQ200_FB_BASE (x) (x + 0x1800000) /* framebuffer */
++#define MQ200_FB_SIZE 0x200000 /* framebuffer size in bytes */
++#define MQ200_REGS_BASE(x) (x + 0x1e00000) /* start of registers area */
++#define MQ200_REGS_SIZE 0x200000 /* registers area size */
++
++#define PMU_OFFSET 0x00000 /* power management */
++#define CPU_OFFSET 0x02000 /* CPU interface */
++#define MIU_OFFSET 0x04000 /* memory controller */
++#define IN_OFFSET 0x08000 /* interrupt controller */
++#define GC_OFFSET 0x0a000 /* graphics controller 1&2 */
++#define GE_OFFSET 0x0c000 /* graphics engine */
++#define FPI_OFFSET 0x0e000 /* flat panel controller */
++#define CP1_OFFSET 0x10000 /* color palette 1 */
++#define DC_OFFSET 0x14000 /* device configuration */
++#define PCI_OFFSET 0x16000 /* PCI configuration */
++#define PSF_OFFSET 0x18000 /* ??? */
++
++
++/****
++ * Registers
++ */
++
++/* power management unit */
++#define PMR(addr) (addr + PCI_OFFSET + 0x40)/* power management
++ register */
++#define PMR_VALUE 0x06210001 /* expected read value of PMR register */
++#define PM00R(addr) (addr + PMU_OFFSET + 0x00) /* power management unit
++ configuration
++ register */
++#define PM01R(addr) (addr + PMU_OFFSET + 0x04) /* D1 state control */
++#define PM02R(addr) (addr + PMU_OFFSET + 0x08) /* d2 state control */
++#define PM06R(addr) (addr + PMU_OFFSET + 0x18) /* PLL 2 programming */
++#define PM07R(addr) (addr + PMU_OFFSET + 0x1c) /* PLL 3 programming */
++
++#define PMCSR(addr) (addr + PCI_OFFSET + 0x44) /* power management
++ control/status
++ register */
++
++/* memory interface unit */
++#define MM00R(addr) (addr + MIU_OFFSET + 0x00)/* MIU interface control
++ 0 */
++#define MM01R(addr) (addr + MIU_OFFSET + 0x04) /* MIU interface control
++ 1 */
++#define MM02R(addr) (addr + MIU_OFFSET + 0x08) /* memory interface
++ control 2 */
++#define MM03R(addr) (addr + MIU_OFFSET + 0x0c) /* memory interface
++ control 3 */
++#define MM04R(addr) (addr + MIU_OFFSET + 0x10) /* memory interface
++ control 4 */
++/* graphics controller 1 module */
++#define GC00R(addr) (addr + GC_OFFSET + 0x00) /* graphics controller 1
++ control */
++#define GC01R(addr) (addr + GC_OFFSET + 0x04) /* graphics controller
++ CRT control */
++#define GC02R(addr) (addr + GC_OFFSET + 0x08) /* horizontal display 1
++ control */
++#define GC03R(addr) (addr + GC_OFFSET + 0x0c) /* vertical display 1
++ control */
++#define GC04R(addr) (addr + GC_OFFSET + 0x10) /* horizontal sync 1
++ control */
++#define GC05R(addr) (addr + GC_OFFSET + 0x14) /* vertical sync 1
++ control */
++#define GC07R(addr) (addr + GC_OFFSET + 0x1c) /* vertical display 1
++ count */
++#define GC08R(addr) (addr + GC_OFFSET + 0x20) /* horizontal window 1
++ control */
++#define GC09R(addr) (addr + GC_OFFSET + 0x24) /* vertical window 1
++ control */
++#define GC0AR(addr) (addr + GC_OFFSET + 0x28) /* alternate horizontal
++ window 1 control */
++#define GC0BR(addr) (addr + GC_OFFSET + 0x2c) /* alternate vertical
++ window 1 control */
++#define GC0CR(addr) (addr + GC_OFFSET + 0x30) /* window 1
++ start address */
++#define GC0DR(addr) (addr + GC_OFFSET + 0x34) /* alternate window 1
++ start address */
++#define GC0ER(addr) (addr + GC_OFFSET + 0x38) /* window 1 stride */
++#define GC0FR(addr) (addr + GC_OFFSET + 0x3c) /* reserved */
++#define GC10R(addr) (addr + GC_OFFSET + 0x40) /* hardware cursor 1
++ position */
++#define GC11R(addr) (addr + GC_OFFSET + 0x44) /* hardware cursor 1
++ start address and
++ offset */
++#define GC12R(addr) (addr + GC_OFFSET + 0x48) /* hardware cursor 1
++ foreground color */
++#define GC13R(addr) (addr + GC_OFFSET + 0x4c) /* hardware cursor 1
++ background color */
++/* graphics engine */
++#define ROP_SRCCOPY 0xCC /* dest = source */
++#define ROP_SRCPAINT 0xEE /* dest = source OR dest */
++#define ROP_SRCAND 0x88 /* dest = source AND dest */
++#define ROP_SRCINVERT 0x66 /* dest = source XOR dest */
++#define ROP_SRCERASE 0x44 /* dest = source AND (NOT dest) */
++#define ROP_NOTSRCCOPY 0x33 /* dest = NOT source */
++#define ROP_NOTSRCERASE 0x11 /* dest = (NOT source) AND (NOT dest) */
++#define ROP_MERGECOPY 0xC0 /* dest = source AND pattern */
++#define ROP_MERGEPAINT 0xBB /* dest = (NOT source) OR dest */
++#define ROP_PATCOPY 0xF0 /* dest = pattern */
++#define ROP_PATPAINT 0xFB /* dest = DPSnoo */
++#define ROP_PATINVERT 0x5A /* dest = pattern XOR dest */
++#define ROP_DSTINVERT 0x55 /* dest = NOT dest */
++#define ROP_BLACKNESS 0x00 /* dest = BLACK */
++#define ROP_WHITENESS 0xFF /* dest = WHITE */
++
++#define GE00R(addr) (addr + GE_OFFSET + 0x00) /* primary drawing command
++ register */
++#define GE01R(addr) (addr + GE_OFFSET + 0x04) /* primary width and
++ height register */
++#define GE02R(addr) (addr + GE_OFFSET + 0x08) /* primary destination
++ address register */
++#define GE03R(addr) (addr + GE_OFFSET + 0x0c) /* primary source XY
++ register */
++#define GE04R(addr) (addr + GE_OFFSET + 0x10) /* primary color compare
++ register */
++#define GE05R(addr) (addr + GE_OFFSET + 0x14) /* primary clip left/top
++ register */
++#define GE06R(addr) (addr + GE_OFFSET + 0x18) /* primary clip
++ right/bottom register
++ */
++#define GE07R(addr) (addr + GE_OFFSET + 0x1c) /* primary source and
++ pattern offset
++ register */
++#define GE08R(addr) (addr + GE_OFFSET + 0x20) /* primary foreground
++ color
++ register/rectangle
++ fill register */
++#define GE09R(addr) (addr + GE_OFFSET + 0x24) /* source stride/offset
++ register */
++#define GE0AR(addr) (addr + GE_OFFSET + 0x28) /* destination stride
++ register and color
++ depth */
++#define GE0BR(addr) (addr + GE_OFFSET + 0x2c) /* image base address
++ register */
++#define GE40R(addr) (addr + GE_OFFSET + 0x100) /* mono pattern register
++ 0 */
++#define GE41R(addr) (addr + GE_OFFSET + 0x104) /* mono pattern register
++ 1 */
++#define GE42R(addr) (addr + GE_OFFSET + 0x108) /* foreground color
++ register */
++#define GE43R(addr) (addr + GE_OFFSET + 0x10c) /* background color
++ register */
++/* color palette */
++#define C1xxR(addr, regno) \
++ (addr + CP1_OFFSET + (regno) * 4) /* graphics controller color
++ palette 1 */
++/* device configuration */
++#define DC00R(addr) (addr + DC_OFFSET + 0x00) /* device configuration
++ register 0 */
++#define DC_RESET 0x4000
++/* PCI configuration space */
++#define PC00R(addr) (addr + PCI_OFFSET + 0x00)/* device ID/vendor ID
++ register */
++/* Flatpanel Control */
++#define FP00R(addr) (addr + FPI_OFFSET + 0x00) /* Flat Panel Control 0 */
++#define FP01R(addr) (addr + FPI_OFFSET + 0x04) /* Flat Panel Output Pin */
++#define FP02R(addr) (addr + FPI_OFFSET + 0x08) /* Flat Panel Gener Purpose
++ Outout Control Register */
++#define FP03R(addr) (addr + FPI_OFFSET + 0x0c) /* General Purpose I/O Port
++ Control Register */
++#define FP04R(addr) (addr + FPI_OFFSET + 0x10) /* STN Panel Control Register */
++#define FP05R(addr) (addr + FPI_OFFSET + 0x14) /* D-STN Half Frame Buffer
++ Control Register -By Guess */
++#define FP0FR(addr) (addr + FPI_OFFSET + 0x3c) /* Pulse Width Modulation
++ Control Register */
++#define FRCTL_PATTERN_COUNT 32
++#define FP10R(addr) (addr + FPI_OFFSET + 0x40) /* Frame-Rate Control Pattern
++ Register */
++#define FP11R(addr) (addr + FPI_OFFSET + 0x44)
++#define FP2FR(addr) (addr + FPI_OFFSET + 0xc0) /* Frame-Rate Control Weight
++ Registers */
++
++
++
++
++/* power management miscellaneous control */
++union pm00r {
++ struct {
++ u32 pll1_n_b5 :1; /* PLL 1 N parameter bit 5 is 0 */
++ u32 reserved_1 :1;
++ u32 pll2_enbl :1; /* PLL 2 enable */
++ u32 pll3_enbl :1; /* PLL 3 enable */
++ u32 reserved_2 :1;
++ u32 pwr_st_ctrl :1; /* power state status control */
++ u32 reserved_3 :2;
++
++ u32 ge_enbl :1; /* graphics engine enable */
++ u32 ge_bsy_gl :1; /* graphics engine force busy (global) */
++ u32 ge_bsy_lcl :1; /* graphics engine force busy (local) */
++ u32 ge_clock :2; /* graphics engine clock select */
++ u32 ge_cmd_fifo :1; /* graphics engine command FIFO reset */
++ u32 ge_src_fifo :1; /* graphics engine CPU source FIFO reset */
++ u32 miu_pwr_seq :1; /* memory interface unit power sequencing
++ enable */
++
++ u32 d3_mem_rfsh :1; /* D3 memory refresh */
++ u32 d4_mem_rfsh :1; /* D4 memory refresh */
++ u32 gpwr_intrvl :2; /* general power sequencing interval */
++ u32 fppwr_intrvl:2; /* flat panel power sequencing interval */
++ u32 gpwr_seq_ctr:1; /* general power sequencing interval control */
++ u32 pmu_tm :1; /* PMU test mode */
++
++ u32 pwr_state :2; /* power state (read only) */
++ u32 pwr_seq_st :1; /* power sequencing active status (read
++ only) */
++ u32 reserved_4 :5;
++ } part;
++ u32 whole;
++};
++
++/* D1 state control */
++union pm01r {
++ struct {
++ u32 osc_enbl :1; /* D1 oscillator enable */
++ u32 pll1_enbl :1; /* D1 PLL 1 enable */
++ u32 pll2_enbl :1; /* D1 PLL 2 enable */
++ u32 pll3_enbl :1; /* D1 PLL 3 enable */
++ u32 miu_enbl :1; /* D1 Memory Interface Unit (MIU) enable */
++ u32 mem_rfsh :1; /* D1 memory refresh enable */
++ u32 ge_enbl :1; /* D1 Graphics Engine (GE) enable */
++ u32 reserved_1 :1;
++
++ u32 crt_enbl :1; /* D1 CRT enable */
++ u32 fpd_enbl :1; /* D1 Flat Panel enable */
++ u32 reserved_2 :6;
++
++ u32 ctl1_enbl :1; /* D1 controller 1 enable */
++ u32 win1_enbl :1; /* D1 window 1 enable */
++ u32 awin1_enbl :1; /* D1 alternate window 1 enable */
++ u32 cur1_enbl :1; /* D1 cursor 1 enable */
++ u32 reserved_3 :4;
++
++ u32 ctl2_enbl :1; /* D1 controller 2 enable */
++ u32 win2_enbl :1; /* D1 window 2 enable */
++ u32 awin2_enbl :1; /* D1 alternate window 2 enable */
++ u32 cur2_enbl :1; /* D1 cursor 2 enable */
++ u32 reserved_4 :4;
++ } part;
++ u32 whole;
++};
++
++/* D2 state control */
++union pm02r {
++ struct {
++ u32 osc_enbl :1; /* D2 oscillator enable */
++ u32 pll1_enbl :1; /* D2 PLL 1 enable */
++ u32 pll2_enbl :1; /* D2 PLL 2 enable */
++ u32 pll3_enbl :1; /* D2 PLL 3 enable */
++ u32 miu_enbl :1; /* D2 Memory Interface Unit (MIU) enable */
++ u32 mem_rfsh :1; /* D2 memory refresh enable */
++ u32 ge_enbl :1; /* D2 Graphics Engine (GE) enable */
++ u32 reserved_1 :1;
++
++ u32 crt_enbl :1; /* D2 CRT enable */
++ u32 fpd_enbl :1; /* D2 Flat Panel enable */
++ u32 reserved_2 :6;
++
++ u32 ctl1_enbl :1; /* D2 controller 1 enable */
++ u32 win1_enbl :1; /* D2 window 1 enable */
++ u32 awin1_enbl :1; /* D2 alternate window 1 enable */
++ u32 cur1_enbl :1; /* D2 cursor 1 enable */
++ u32 reserved_3 :4;
++
++ u32 ctl2_enbl :1; /* D2 controller 2 enable */
++ u32 win2_enbl :1; /* D2 window 2 enable */
++ u32 awin2_enbl :1; /* D2 alternate window 2 enable */
++ u32 cur2_enbl :1; /* D2 cursor 2 enable */
++ u32 reserved_4 :4;
++ } part;
++ u32 whole;
++};
++
++/* PLL 2 programming */
++union pm06r {
++ struct {
++ u32 clk_src :1; /* PLL 2 reference clock source */
++ u32 bypass :1; /* PLL 2 bypass */
++ u32 reserved_1 :2;
++ u32 p_par :3; /* PLL 2 P parameter */
++ u32 reserved_2 :1;
++
++ u32 n_par :5; /* PLL 2 N parameter */
++ u32 reserved_3 :3;
++
++ u32 m_par :8; /* PLL 2 M parameter */
++
++ u32 reserved_4 :4;
++ u32 trim :4; /* PLL 2 trim value */
++ } part;
++ u32 whole;
++};
++
++/* PLL 3 programming */
++union pm07r {
++ struct {
++ u32 clk_src :1; /* PLL 3 reference clock source */
++ u32 bypass :1; /* PLL 3 bypass */
++ u32 reserved_1 :2;
++ u32 p_par :3; /* PLL 3 P parameter */
++ u32 reserved_2 :1;
++
++ u32 n_par :5; /* PLL 3 N parameter */
++ u32 reserved_3 :3;
++
++ u32 m_par :8; /* PLL 3 M parameter */
++
++ u32 reserved_4 :4;
++ u32 trim :4; /* PLL 3 trim value */
++ } part;
++ u32 whole;
++};
++
++
++
++/* MIU interface control 1 */
++union mm00r {
++ struct {
++ u32 miu_enbl :1; /* MIU enable bit */
++ u32 mr_dsbl :1; /* MIU reset disable bit */
++ u32 edr_dsbl :1; /* embedded DRAM reset disable bit */
++ u32 reserved_1 :29;
++ } part;
++ u32 whole;
++};
++
++/* MIU interface control 2 */
++union mm01r {
++ struct {
++ u32 mc_src :1; /* memory clock source */
++ u32 msr_enbl :1; /* memory slow refresh enable bit */
++ u32 pb_cpu :1; /* page break enable for CPU */
++ u32 pb_gc1 :1; /* page break enable for GC1 */
++ u32 pb_gc2 :1; /* page break enable for GC2 */
++ u32 pb_stn_r :1; /* page break enable for STN read */
++ u32 pb_stn_w :1; /* page break enable for STN write */
++ u32 pb_ge :1; /* page break enable for GE */
++ u32 reserved_1 :4;
++ u32 mr_interval :14; /* normal memory refresh time interval */
++ u32 reserved_2 :4;
++ u32 edarm_enbl :1; /* embedded DRAM auto-refresh mode enable */
++ u32 eds_enbl :1; /* EDRAM standby enable for EDRAM normal
++ mode operation */
++ } part;
++ u32 whole;
++};
++
++/* memory interface control 3 */
++union mm02r {
++ struct {
++ u32 bs_ :2;
++ u32 bs_stnr :2; /* burst count for STN read memory cycles */
++ u32 bs_stnw :2; /* burst count for STN write memroy cycles */
++ u32 bs_ge :2; /* burst count for graphics engine
++ read/write memroy cycles */
++ u32 bs_cpuw :2; /* burst count for CPU write memory cycles */
++ u32 fifo_gc1 :4; /* GC1 display refresh FIFO threshold */
++ u32 fifo_gc2 :4; /* GC2 display refresh FIFO threshold */
++ u32 fifo_stnr :4; /* STN read FIFO threshold */
++ u32 fifo_stnw :4; /* STN write FIFO threshold */
++ u32 fifo_ge_src :3; /* GE source read FIFO threshold */
++ u32 fifo_ge_dst :3; /* GE destination read FIFO threshold */
++ } part;
++ u32 whole;
++};
++
++/* memory interface control 4 */
++union mm03r {
++ struct {
++ u32 rd_late_req :1; /* read latency request */
++ u32 reserved_1 :31;
++ } part;
++ u32 whole;
++};
++
++/* memory interface control 5 */
++union mm04r {
++ struct {
++ u32 latency :3; /* EDRAM latency */
++ u32 dmm_cyc :1; /* enable for the dummy cycle insertion
++ between read and write cycles */
++ u32 pre_dmm_cyc :1; /* enable for the dummy cycle insertion
++ between read/write and precharge cycles
++ for the same bank */
++ u32 reserved_1 :3;
++ u32 bnk_act_cls :2; /* bank activate command to bank close
++ command timing interval control */
++ u32 bnk_act_rw :1; /* bank activate command to read/wirte
++ command timing interval control */
++ u32 bnk_cls_act :1; /* bank close command to bank activate
++ command timing interval control */
++ u32 trc :1; /* row cycle time */
++ u32 reserved_2 :3;
++ u32 delay_r :2; /* programmable delay for read clock */
++ u32 delay_m :2; /* programmable delay for internal memory
++ clock */
++ } part;
++ u32 whole;
++};
++
++/* graphics controller 1 register */
++union gc00r {
++ struct {
++ u32 ctl_enbl :1; /* Controller 1 Enable */
++ u32 hc_reset :1; /* Horizontal Counter 1 Reset */
++ u32 vc_reset :1; /* Vertical Counter 1 Reset */
++ u32 iwin_enbl :1; /* Image Window 1 Enable */
++ u32 gcd :4; /* Graphics Color Depth (GCD) */
++
++ u32 hc_enbl :1; /* Hardware Cursor 1 Enable */
++ u32 reserved_1 :2;
++ u32 aiwin_enbl :1; /* Alternate Image Window Enable */
++ u32 agcd :4; /* Alternate Graphics Color Depth (AGCD) */
++
++ u32 g1rclk_src :2; /* G1RCLK Source */
++ u32 tm0 :1; /* Test Mode 0 */
++ u32 tm1 :1; /* Test Mode 1 */
++ u32 fd :3; /* G1MCLK First Clock Divisor (FD1) */
++ u32 reserved_2 :1;
++
++ u32 sd :8; /* G1MCLK Second Clock Divisor (SD1) */
++ } part;
++ u32 whole;
++};
++
++/* graphics controller CRT control */
++union gc01r {
++ struct {
++ u32 dac_enbl :2; /* CRT DAC enable */
++ u32 hsync_out :1; /* CRT HSYNC output during power down mode */
++ u32 vsync_out :1; /* CRT VSYNC output during power down mode */
++ u32 hsync_ctl :2; /* CRT HSYNC control */
++ u32 vsync_ctl :2; /* CRT VSYNC control */
++ /**/
++ u32 hsync_pol :1; /* CRT HSYNC polarity */
++ u32 vsync_pol :1; /* CRT VSYNC polarity */
++ u32 sync_p_enbl :1; /* sync pedestal enable */
++ u32 blnk_p_enbl :1; /* blank pedestal enable */
++ u32 c_sync_enbl :1; /* composite sync enable */
++ u32 vref_sel :1; /* VREF select */
++ u32 mn_sns_enbl :1; /* monitor sense enable */
++ u32 ct_out_enbl :1; /* constant output enable */
++ /**/
++ u32 dac_out_lvl :8; /* monitor sense DAC output level */
++ /**/
++ u32 blue_dac_r :1; /* blue DAC sense result */
++ u32 green_dac_r :1; /* green DAC sense result */
++ u32 red_dac_r :1; /* red DAC sense result */
++ u32 reserved_1 :1;
++ u32 mon_col_sel :1; /* mono/color monitor select */
++ u32 reserved_2 :3;
++ } part;
++ u32 whole;
++};
++
++/* horizontal display 1 control */
++union gc02r {
++ struct {
++ u32 hd1t :12; /* horizontal display 1 total */
++ u32 reserved_1 :4;
++
++ u32 hd1e :12; /* horizontal display 1 end */
++ u32 reserved_2 :4;
++ } part;
++ u32 whole;
++};
++
++/* vertical display 1 control */
++union gc03r {
++ struct {
++ u32 vd1t :12; /* vertical display 1 total */
++ u32 reserved_1 :4;
++
++ u32 vd1e :12; /* vertical display 1 end */
++ u32 reserved_2 :4;
++ } part;
++ u32 whole;
++};
++
++/* horizontal sync 1 control */
++union gc04r {
++ struct {
++ u32 hs1s :12; /* horizontal sync 1 start */
++ u32 reserved_1 :4;
++
++ u32 hs1e :12; /* horizontal sync 1 end */
++ u32 reserved_2 :4;
++ } part;
++ u32 whole;
++};
++
++/* vertical sync 1 control */
++union gc05r {
++ struct {
++ u32 vs1s :12; /* vertical sync 1 start */
++ u32 reserved_1 :4;
++
++ u32 vs1e :12; /* vertical sync 1 end */
++ u32 reserved_2 :4;
++ } part;
++ u32 whole;
++};
++
++/* vertical display 1 count */
++union gc07r {
++ struct {
++ u32 vd_cnt :12; /* vertical display 1 count */
++ u32 reverved_1 :20;
++ } part;
++ u32 whole;
++};
++
++/* horizontal window 1 control */
++union gc08r {
++ struct {
++ u32 hw1s :12; /* horizontal window 1 start (HW1S) */
++ u32 reserved_1 :4;
++
++ u32 hw1w :12; /* horizontal window 1 width (HW1W) */
++ u32 w1ald :4; /* window 1 additional line data */
++ } part;
++ u32 whole;
++};
++
++/* vertical window 1 control */
++union gc09r {
++ struct {
++ u32 vw1s :12; /* vertical window 1 start */
++ u32 reserved_1 :4;
++ u32 vw1h :12; /* vertical window 1 height */
++ u32 reserved_2 :4;
++ } part;
++ u32 whole;
++};
++
++/* window 1 start address */
++union gc0cr {
++ struct {
++ u32 w1sa :21; /* window 1 start address */
++ u32 reserved_1 :11;
++ } part;
++ u32 whole;
++};
++
++/* window 1 stride */
++union gc0er {
++ struct {
++ s16 w1st; /* window 1 stride */
++ s16 aw1st; /* alternate window 1 stride */
++ } part;
++ u32 whole;
++};
++
++/* hardware cursor 1 position */
++union gc10r {
++ struct {
++ u32 hc1s :12; /* horizontal cursor 1 start */
++ u32 reserved_1 :4;
++ u32 vc1s :12; /* vertical cursor 1 start */
++ u32 reserved_2 :4;
++ } part;
++ u32 whole;
++};
++
++/* hardware cursor 1 start address and offset */
++union gc11r {
++ struct {
++ u32 hc1sa :11; /* hardware cursor 1 start address */
++ u32 reserved_1 :5;
++ u32 hc1o :6; /* horizontal cursor 1 offset */
++ u32 reserved_2 :2;
++ u32 vc1o :6; /* vertical cursor 1 offset */
++ u32 reserved_3 :2;
++ } part;
++ u32 whole;
++};
++
++/* hardware cursor 1 foreground color */
++union gc12r {
++ struct {
++ u32 hc1fc :24; /* hardware cursor 1 foreground color */
++ u32 reserved_1 :8;
++ } part;
++ u32 whole;
++};
++
++/* hardware cursor 1 background color */
++union gc13r {
++ struct {
++ u32 hc1bc :24; /* hardware cursor 1 background color */
++ u32 reserved_1 :8;
++ } part;
++ u32 whole;
++};
++
++/* primary drawing command register */
++union ge00r {
++ struct {
++ u32 rop :8; /* raster operation */
++ /**/
++ u32 cmd_typ :3; /* command type */
++ u32 x_dir :1; /* x direction */
++ u32 y_dir :1; /* y direction */
++ u32 src_mem :1; /* source memory */
++ u32 mon_src :1; /* mono source */
++ u32 mon_ptn :1; /* mono pattern */
++ /**/
++ u32 dst_trns_e :1; /* destination transparency enable */
++ u32 dst_trns_p :1; /* destination transparency polarity */
++ u32 mon_trns_e :1; /* mono source or mono pattern transparency
++ enable */
++ u32 mon_trns_p :1; /* mono transparency polarity */
++ u32 mod_sel :1; /* memory to screen or off screen to screen
++ mode select */
++ u32 alpha_sel :2; /* Alpha byte mask selection */
++ u32 sol_col :1; /* solid color */
++ /**/
++ u32 stride_eq :1; /* source stride is equal to destination
++ stride */
++ u32 rop2_sel :1; /* ROP2 code selection */
++ u32 clipping :1; /* enable clipping */
++ u32 auto_exec :1; /* auto execute */
++ u32 reserved_1 :4;
++ } part;
++ u32 whole;
++};
++
++/* primary width and height register */
++union ge01r {
++ struct {
++ u32 width :12; /* source/destination window width */
++ u32 reserved_1 :4;
++
++ u32 height :12; /* source/destination window height */
++ u32 reserved_2 :1;
++ u32 reserved_3 :3;
++ } bitblt;
++ struct {
++ u32 dm :17;
++ u32 axis_major :12;
++ u32 x_y :1; /* x-major or y-major */
++ u32 last_pix :1; /* decision to draw or not to draw the last
++ pixel of the line */
++ u32 reserved_1 :1;
++ } bresenham;
++ u32 whole;
++};
++
++/* primary destination address register */
++union ge02r {
++ struct {
++ u32 dst_x :12; /* destination x position */
++ u32 reserved_1 :1;
++ u32 h_offset :3; /* mono/color pattern horizontal offset */
++
++ u32 dst_y :12; /* destination y position */
++ u32 reserved_2 :1;
++ u32 v_offset :3; /* mono/color pattern vertical offset */
++ } window;
++ struct {
++ u32 x :12; /* starting x coordinate */
++ u32 dm :17; /* 17 bits major-axis delta */
++ u32 reserved_1 :3;
++ } line;
++ u32 whole;
++};
++
++/* source XY register/line draw starting Y coordinate and mintor axis delta */
++union ge03r {
++ struct {
++ u32 src_x :12; /* source X position */
++ u32 reserved_1 :4;
++
++ u32 src_y :12; /* source Y position */
++ u32 reserved_2 :4;
++ } window;
++ struct {
++ u32 start_y :12; /* starting Y coordinate */
++ u32 dn :17; /* 17 bits minor-axis delta */
++ u32 reserved_1 :3;
++ } line;
++ u32 whole;
++};
++
++/* clip left/top register */
++union ge05r {
++ struct {
++ u32 left :12; /* left edge of clipping rectangle */
++ u32 reserved_1 :4;
++
++ u32 top :12; /* top edge of clipping rectangle */
++ u32 reserved_2 :4;
++ } part;
++ u32 whole;
++};
++
++/* source stride/offset register */
++union ge09r {
++ struct {
++ u32 src_strid :12; /* source line stride */
++ u32 reserved_1 :13;
++ u32 strt_bit :3; /* initial mono source bit offset */
++ u32 strt_byte :3; /* initial mono/color source byte offset */
++ u32 reserved_2 :1;
++ } line;
++ struct {
++ u32 strt_bit :5; /* initial mono source bit offset */
++ u32 reserved_1 :1;
++ u32 amount :10; /* number of 16 bytes amount that MIU need
++ to fetch from frame buffer */
++
++ u32 reserved_2 :9;
++ u32 bit_spc :7; /* bit space between lines */
++ } pack_mono;
++ struct {
++ u32 strt_bit :3; /* initial mono source bit offset */
++ u32 strt_byte :3; /* initial mono/color source byte offset */
++ u32 amount :10; /* number of 16 bytes amount that MIU need
++ to fetch from frame buffer */
++
++ u32 reserved_1 :9;
++ u32 bit_spc :3; /* bit space between lines */
++ u32 byt_spc :4; /* byte space between lines */
++ } pack_color;
++ u32 whole;
++};
++
++/* destination stride register and color depth */
++union ge0ar {
++ struct {
++ u32 dst_strid :12; /* destination line stride and color depth */
++ u32 reserved_1 :18;
++ u32 col_dpth :2; /* color depth */
++ } part;
++ u32 whole;
++};
++
++/* graphics controller color pallete */
++union c1xxr {
++ struct {
++ u8 red; /* red color pallete */
++ u8 green; /* green/gray color pallete */
++ u8 blue; /* blue color palette */
++ u8 reserved_1;
++ } part;
++ u32 whole;
++};
++
++/* devicee configuration register 0 */
++union dc00r {
++ struct {
++ u32 osc_bypass :1; /* oscillator bypass */
++ u32 osc_enbl :1; /* oscillator enable */
++ u32 pll1_bypass :1; /* PLL1 bypass */
++ u32 pll1_enbl :1; /* PLL1 enable */
++ u32 pll1_p_par :3; /* PLL1 P parameter */
++ u32 cpu_div :1; /* CPU interface clock divisor */
++ u32 pll1_n_par :5; /* PLL1 N parameter */
++ u32 saisc :1; /* StrongARM interface synchronizer control */
++ u32 s_chp_reset :1; /* software chip reset */
++ u32 mem_enbl :1; /* memory standby enable */
++ u32 pll1_m_par :8; /* PLL 1 M parameter */
++ u32 osc_shaper :1; /* oscillator shaper disable */
++ u32 fast_pwr :1; /* fast power sequencing */
++ u32 osc_frq :2; /* oscillator frequency select */
++ u32 pll1_trim :4; /* PLL 1 trim value */
++ } part;
++ u32 whole;
++};
++
++/* device ID/vendor ID register */
++union pc00r {
++ struct {
++ u16 device; /* device ID */
++ u16 vendor; /* vendor ID */
++ } part;
++ u32 whole;
++};
++
++/* Flat Panel Control Register */
++union fp00r {
++ struct {
++ u32 flatp_enbl : 2; /* Flat Panel Interface Enable */
++ u32 flatp_type : 2; /* Flat Panel Type */
++ u32 mono : 1; /* Mono/Color Panel Select */
++ u32 flatp_intf : 3; /* Flat Panel Interface */
++ u32 dither_pat : 2; /* Dither Pattern */
++ u32 reserved : 2; /* Reserved Must Be 0*/
++ u32 dither_col : 3; /* Dither Base Color */
++ u32 alt_win_ctl: 1; /* Alternate Window Control */
++ u32 frc_ctl : 2; /* FRC Control */
++ u32 dither_adj1: 6; /* Dither Pattern Adjust 1 */
++ u32 dither_adj2: 3; /* Dither Pattern Adjust 2 */
++ u32 dither_adj3: 1; /* Dither Pattern Adjust 3 */
++ u32 test_mode0 : 1; /* Test Mode 0 */
++ u32 test_mode1 : 1; /* Test Mode 1 */
++ u32 test_mode2 : 1; /* Test Mode 2 */
++ u32 test_mode3 : 1; /* Test Mode 3 */
++ } part;
++ u32 whole;
++};
++
++union fp01r {
++ struct {
++ u32 dummy;
++ } part;
++ u32 whole;
++};
++
++union fp02r {
++ struct {
++ u32 dummy;
++ } part;
++ u32 whole;
++};
++
++union fp03r {
++ struct {
++ u32 dummy;
++ } part;
++ u32 whole;
++};
++
++union fp04r {
++ struct {
++ u32 dummy;
++ } part;
++ u32 whole;
++};
++
++union fp05r {
++ struct {
++ u32 dummy;
++ } part;
++ u32 whole;
++};
++
++union fp0fr {
++ struct {
++ u32 dummy;
++ } part;
++ u32 whole;
++};
++
++
++
++
++/****
++ * Others
++ */
++
++#define CHIPNAME "MQ-200"
++
++extern void mq200_external_setpal(unsigned regno, unsigned long color, unsigned long addr);
++extern void mq200_external_setqmode(struct mq200_monitor_info*, unsigned long, spinlock_t *);
++extern void mq200_external_offdisplay(unsigned long);
++extern void mq200_external_ondisplay (unsigned long);
++extern int mq200_external_probe(unsigned long);
++
++
++
++#endif
+diff -uNr linux-2.6.20.vanilla/drivers/video/mq200/mq_external.c linux-2.6.20/drivers/video/mq200/mq_external.c
+--- linux-2.6.20.vanilla/drivers/video/mq200/mq_external.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.20/drivers/video/mq200/mq_external.c 2007-02-11 16:41:09.000000000 +0100
+@@ -0,0 +1,427 @@
++/*
++ * Copyright (C) 2005 Holger Hans Peter Freyther
++ *
++ * Based ON:
++ *
++ * linux/drivers/video/mq200fb.c -- MQ-200 for a frame buffer device
++ * based on linux/driver/video/pm2fb.c
++ *
++ * Copyright (C) 2000 Lineo, Japan
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ */
++
++#include <asm/types.h>
++#include <asm/io.h>
++#include <linux/delay.h>
++#include <linux/spinlock.h>
++
++#include "mq200_data.h"
++
++
++#if 1
++#define PRINTK(args...) printk(args)
++#else
++#define PRINTK(args...)
++#endif
++
++
++/****
++ * power state transition to "state".
++ */
++static void
++power_state_transition(unsigned long register_base, int state)
++{
++ int i;
++ writel(state, PMCSR(register_base));
++ for (i = 1; ; i++) {
++ udelay(100);
++ if ((readl(PMCSR(register_base)) & 0x3) == state) {
++ break;
++ }
++ }
++}
++
++
++/****
++ * device configuration initialization.
++ */
++static void
++dc_reset(unsigned long register_base)
++{
++ union dc00r dc00r;
++
++ /* Reset First */
++ dc00r.whole = DC_RESET;
++ writel(dc00r.whole, DC00R(register_base));
++ udelay(10);
++
++
++ dc00r.whole = 0xEF2082A;
++ writel(dc00r.whole, DC00R(register_base));
++ udelay(5);
++ PRINTK(CHIPNAME ": DC00R = %xx\n", readl(DC00R(register_base)));
++}
++
++
++/****
++ * initialize memory interface unit.
++ */
++static void
++miu_reset(unsigned long register_base)
++{
++ union mm00r mm00r;
++ union mm01r mm01r;
++ union mm02r mm02r;
++ union mm03r mm03r;
++ union mm04r mm04r;
++
++ /* MIU interface control 1 */
++ mm00r.whole = 0x4;
++ writel(mm00r.whole, MM00R(register_base));
++ udelay(5);
++ writel(0, MM00R(register_base));
++ udelay(50);
++
++ /* MIU interface control 2
++ * o PLL 1 output is used as memory clock source.
++ */
++ mm01r.whole = 0x4143e086;
++ writel(mm01r.whole, MM01R(register_base));
++
++ /* memory interface control 3 */
++ mm02r.whole = 0x6d6aabff;
++ writel(mm02r.whole, MM02R(register_base));
++
++ /* memory interface control 5 */
++ mm04r.whole = 0x10d;
++ writel(mm04r.whole, MM04R(register_base));
++
++ /* memory interface control 4 */
++ mm03r.whole = 0x1;
++ writel(mm03r.whole, MM03R(register_base));
++ mdelay(10);
++
++ /* MIU interface control 1 */
++ mm00r.whole = 0x3;
++ writel(mm00r.whole, MM00R(register_base));
++ mdelay(50);
++}
++
++/****
++ *
++ */
++static
++void fpctrl_reset(unsigned long addr)
++{
++ /*
++ * We're in D0 State, let us set the FPCTRL
++ */
++ union fp00r fp00r;
++ union fp01r fp01r;
++ union fp02r fp02r;
++ union fp03r fp03r;
++ union fp04r fp04r;
++ union fp0fr fp0fr;
++
++ fp00r.whole = 0x6320;
++ writel(fp00r.whole, FP00R(addr));
++
++ fp01r.whole = 0x20;
++ writel(fp01r.whole, FP01R(addr));
++
++ fp04r.whole = 0xBD0001;
++ writel(fp04r.whole, FP04R(addr));
++
++ /* Set Flat Panel General Purpose register first */
++ fp02r.whole = 0x0;
++ writel(fp02r.whole, FP02R(addr));
++
++ fp03r.whole = 0x0;
++ writel(fp03r.whole, FP03R(addr));
++
++ fp0fr.whole = 0xA16c44;
++ writel(fp0fr.whole, FP0FR(addr));
++
++
++ /* Set them again */
++ fp02r.whole = 0x0;
++ writel(fp02r.whole, FP02R(addr));
++
++ fp03r.whole = 0x0;
++ writel(fp03r.whole, FP03R(addr));
++}
++
++
++/****
++ * initialize power management unit.
++ */
++static void
++pmu_reset(unsigned long register_base)
++{
++ union pm00r pm00r;
++ union pm01r pm01r;
++ union pm02r pm02r;
++// union pm06r pm06r;
++// union pm07r pm07r;
++
++ /* power management miscellaneous control
++ * o GE is driven by PLL 1 clock.
++ */
++ pm00r.whole = 0xc0900;
++ writel(pm00r.whole, PM00R(register_base));
++
++ /* D1 state control */
++ pm01r.whole = 0x5000271;
++ writel(pm01r.whole, PM01R(register_base));
++
++ /* D2 state control */
++ pm02r.whole = 0x271;
++ writel(pm02r.whole, PM02R(register_base));
++
++#if 0
++ /* PLL 2 programming */
++ pm06r.whole = 0xE90830;
++ writel(pm06r.whole, PM06R(register_base));
++
++ /* PLL 3 programming */
++ pm07r.whole = 0xE90830;
++ writel(pm07r.whole, PM07R(register_base));
++#endif
++}
++
++/****
++ * initialize graphics controller 1.
++ */
++static void
++gc1_reset(unsigned long register_base, spinlock_t *lock )
++{
++ unsigned long flags;
++ union gc00r gc00r;
++ union gc01r gc01r;
++ union gc02r gc02r;
++ union gc03r gc03r;
++ union gc04r gc04r;
++ union gc05r gc05r;
++ union gc08r gc08r;
++ union gc09r gc09r;
++// union gc0er gc0er;
++// union gc11r gc11r;
++ union pm00r pm00r;
++ union pm06r pm06r;
++
++ spin_lock_irqsave(lock, flags);
++
++ /* graphics controller CRT control */
++ gc01r.whole = 0x800;
++ writel(gc01r.whole, GC01R(register_base));
++
++ /* horizontal display 1 control */
++ gc02r.whole = 0x320041e;
++ writel(gc02r.whole, GC02R(register_base));
++
++ /* vertical display 1 control */
++ gc03r.whole = 0x2570273;
++ writel(gc03r.whole, GC03R(register_base));
++
++ /* horizontal sync 1 control */
++ gc04r.whole = 0x3c70347;
++ writel(gc04r.whole, GC04R(register_base));
++
++ /* vertical sync 1 control */
++ gc05r.whole = 0x25d0259;
++ writel(gc05r.whole, GC05R(register_base));
++
++ /* horizontal window 1 control */
++ gc08r.whole = 0x131f0000;
++ writel(gc08r.whole, GC08R(register_base));
++
++ /* vertical window 1 control */
++ gc09r.whole = 0x2570000;
++ writel(gc09r.whole, GC09R(register_base));
++
++#if 0
++ /* alternate horizontal window 1 control */
++ writel(0, GC0AR(register_base));
++
++ /* alternate vertical window 1 control */
++ writel(0, GC0BR(register_base));
++
++ /* window 1 start address */
++ writel(0x2004100, GC0CR(register_base));
++
++ /* alternate window 1 start address */
++ writel(0, GC0DR(register_base));
++
++ /* window 1 stride */
++ gc0er.whole = 0x5100048;
++ writel(gc0er.whole, GC0ER(register_base));
++
++ /* reserved register - ??? - */
++ writel(0x31f, GC0FR(register_base));
++#endif
++
++#if 0
++ /* hardware cursor 1 position */
++ writel(0, GC10R(register_base));
++
++ /* hardware cursor 1 start address and offset */
++ gc11r.whole = 0x5100048;
++ writel(gc11r.whole, GC11R(register_base));
++
++ /* hardware cursor 1 foreground color */
++ writel(0x00ffffff, GC12R(register_base));
++
++ /* hardware cursor 1 background color */
++ writel(0x00000000, GC13R(register_base));
++#endif
++
++ /* PLL 2 programming */
++ pm06r.whole = 0xE90830;
++ writel(pm06r.whole, PM06R(register_base));
++
++
++ /* graphics controller 1 register
++ * o GC1 clock source is PLL 2.
++ * o hardware cursor is disabled.
++ */
++ gc00r.whole = 0x10200C8;
++ writel(gc00r.whole, GC00R(register_base));
++
++ /*
++ * Enable PLL2 in the PM Register
++ */
++ pm00r.whole = readl(PM00R(register_base));
++ pm00r.part.pll2_enbl = 0x1;
++ writel(pm00r.whole, PM00R(register_base));
++
++ spin_unlock_irqrestore(lock, flags);
++}
++
++
++/****
++ * initialize graphics engine.
++ */
++static void
++ge_reset(unsigned long register_base)
++{
++ /* drawing command register */
++ writel(0, GE00R(register_base));
++
++ /* promary width and height register */
++ writel(0, GE01R(register_base));
++
++ /* primary destination address register */
++ writel(0, GE02R(register_base));
++
++ /* primary source XY register */
++ writel(0, GE03R(register_base));
++
++ /* primary color compare register */
++ writel(0, GE04R(register_base));
++
++ /* primary clip left/top register */
++ writel(0, GE05R(register_base));
++
++ /* primary clip right/bottom register */
++ writel(0, GE06R(register_base));
++
++ /* primary source and pattern offset register */
++ writel(0, GE07R(register_base));
++
++ /* primary foreground color register/rectangle fill color depth */
++ writel(0, GE08R(register_base));
++
++ /* source stride/offset register */
++ writel(0, GE09R(register_base));
++
++ /* destination stride register and color depth */
++ writel(0, GE0AR(register_base));
++
++ /* image base address register */
++ writel(0, GE0BR(register_base));
++}
++
++
++/****
++ * initialize Color Palette 1.
++ */
++static void
++cp1_reset(unsigned long addr_info)
++{
++ int i;
++
++ for (i = 0; i < 256; i++)
++ writel(0, C1xxR(addr_info, i));
++}
++
++
++
++
++/*
++ * Below functions are called from the skeleton
++ */
++void mq200_external_setpal(unsigned regno, unsigned long color, unsigned long addr)
++{
++ writel(color,C1xxR(addr,regno));
++}
++
++void mq200_external_setqmode(struct mq200_monitor_info* info,
++ unsigned long addr, spinlock_t *lock)
++{
++ dc_reset(addr); /* device configuration */
++
++ power_state_transition(addr, 0); /* transition to D0 state */
++ pmu_reset(addr); /* power management unit */
++ miu_reset(addr); /* memory interface unit */
++ ge_reset(addr); /* graphics engine */
++ fpctrl_reset(addr); /* reset the panel settings */
++ gc1_reset(addr, lock); /* graphics controller 1 */
++ cp1_reset(addr); /* color palette 1 */
++ mq200_external_ondisplay(addr);
++}
++
++void mq200_external_offdisplay(unsigned long addr)
++{
++ /*
++ * Move the MQ200 to D3 mode
++ */
++ power_state_transition(addr, 3);
++}
++
++/**
++ * to be called after mq200_external_setqmode
++ */
++void mq200_external_ondisplay (unsigned long addr)
++{
++ /*
++ * Set the framebuffer details
++ */
++ #warning FIX HERE AS WELL
++ union gc00r gc00r;
++ union fp00r fp00r;
++ gc00r.whole = readl(GC00R(addr));
++ fp00r.whole = readl(FP00R(addr));
++
++ if(!(gc00r.whole & 0x1)) {
++ gc00r.whole |= 1;
++ writel(gc00r.whole, GC00R(addr));
++ }
++
++ fp00r.whole |= 0x01;
++ writel(fp00r.whole, FP00R(addr));
++}
++
++int mq200_external_probe(unsigned long addr)
++{
++ union pc00r pc00r;
++ if(readl(PMR(addr)) != PMR_VALUE)
++ return 0;
++
++ pc00r.whole = readl(PC00R(addr));
++ printk(KERN_INFO "mq200 video driver found Vendor:%d Device:%d\n",
++ pc00r.part.device, pc00r.part.vendor);
++ return 1;
++}
+diff -uNr linux-2.6.20.vanilla/drivers/video/mq200/mq_skeleton.c linux-2.6.20/drivers/video/mq200/mq_skeleton.c
+--- linux-2.6.20.vanilla/drivers/video/mq200/mq_skeleton.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.20/drivers/video/mq200/mq_skeleton.c 2007-02-11 16:41:09.000000000 +0100
+@@ -0,0 +1,401 @@
++/*
++ * Author: Holger Hans Peter Freyther
++ *
++ *
++ * This implements the frame buffer driver interface to communicate
++ * with the kernel.
++ * It uses the mq200 routines from the ucLinux driver from Lineo
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/autoconf.h>
++#include <linux/platform_device.h>
++#include <linux/module.h>
++#include <linux/fb.h>
++#include <linux/types.h>
++#include <linux/spinlock.h>
++
++#include "mq200_data.h"
++
++#if CONFIG_SA1100_SIMPAD
++/*
++ * Siemens SIMpad specefic data
++ */
++#include <asm/arch/simpad.h>
++#include <asm/arch/hardware.h>
++
++#define MQ200_REGIONS simpad_mq200_regions
++#define MQ200_MONITOR simpad_mq200_panel
++
++static struct mq200_io_regions simpad_mq200_regions = {
++ .fb_size = MQ200_FB_SIZE,
++ .phys_mmio_base = 0x4be00000,
++ .virt_mmio_base = 0xf2e00000,
++ .phys_fb_base = 0x4b800000,
++ .virt_fb_base = 0xf2800000,
++};
++
++static struct mq200_monitor_info simpad_mq200_panel = {
++ .horizontal_res = 800,
++ .vertical_res = 600,
++ .depth = 16,
++ .refresh = 60,
++ .line_length = 1600,
++ .flags = 0x00130004,
++};
++
++extern long get_cs3_shadow(void);
++extern void set_cs3_bit(int value);
++extern void clear_cs3_bit(int value);
++#endif
++
++
++
++struct mq200_info {
++ struct fb_info fb_info;
++ struct mq200_io_regions io_regions;
++ struct mq200_monitor_info monitor_info;
++
++ /* palette */
++ u32 pseudo_palette[17]; /* 16 colors + 1 in reserve not that well documented... */
++ spinlock_t lock;
++};
++
++
++
++static int mq200_blank( int blank_mode, struct fb_info *info )
++{
++#ifdef CONFIG_SA1100_SIMPAD
++ if(blank_mode ){
++ clear_cs3_bit(DISPLAY_ON);
++ }else {
++ set_cs3_bit(DISPLAY_ON);
++ }
++#endif
++ return 0;
++}
++
++
++static int mq200_check_var(struct fb_var_screeninfo *var,
++ struct fb_info *info )
++{ /* TODO do we need sanity checks here */
++ return 0;
++}
++
++
++static int mq200_set_par( struct fb_info *info )
++{
++ /* TODO set paraemeter */
++ return 0;
++}
++
++static int mq200_setcolreg(unsigned regno, unsigned red, unsigned green,
++ unsigned blue, unsigned transp,
++ struct fb_info *info )
++{
++ struct mq200_info *p;
++ unsigned long color;
++ u32* pal = info->pseudo_palette;
++
++ p = info->par;
++
++ if(regno > 255 )
++ return 1;
++
++ switch( info->var.bits_per_pixel ){
++ case 16:
++ pal[regno] =
++ ((red & 0xf800) >> 0) |
++ ((green & 0xf800) >> 5) | ((blue & 0xf800) >> 11);
++ break;
++ case 24:
++ pal[regno] =
++ ((red & 0xff00) << 8) |
++ ((green & 0xff00)) | ((blue & 0xff00) >> 8);
++ break;
++ case 32:
++ pal[regno] =
++ ((red & 0xff00) >> 8) |
++ ((green & 0xff00)) | ((blue & 0xff00) << 8);
++ break;
++ default:
++ break;
++ }
++
++ red &= 0xFF;
++ green &= 0xFF;
++ blue &= 0xFF;
++
++ color = red | (green << 8) | (blue << 16);
++ mq200_external_setpal(regno, color, p->io_regions.virt_mmio_base);
++
++ return 0;
++}
++
++
++
++
++static struct fb_ops mq200_ops = {
++ .owner = THIS_MODULE,
++ .fb_check_var = mq200_check_var,
++ .fb_set_par = mq200_set_par,
++ .fb_setcolreg = mq200_setcolreg,
++#ifdef FB_SOFT_CURSOR
++ .fb_cursor = soft_cursor, /* FIXME use hardware cursor */
++#endif
++ .fb_fillrect = cfb_fillrect,
++ .fb_copyarea = cfb_copyarea,
++ .fb_imageblit = cfb_imageblit,
++ .fb_blank = mq200_blank,
++};
++
++
++/*********************************************************************
++ *
++ * Device driver and module init code
++ * this will register to the fb layer later
++ *
++ *********************************************************************/
++static void mq200_internal_init_color( struct fb_bitfield* red,
++ struct fb_bitfield* green,
++ struct fb_bitfield* blue,
++ int bpp )
++{
++ switch ( bpp )
++ {
++ case 16:
++ red->offset = 11;
++ green->offset = 5;
++ blue->offset = 0;
++
++ red->length = 5;
++ green->length = 6;
++ blue->length = 5;
++ break;
++ case 24:
++ red->offset = 16;
++ green->offset = 8;
++ blue->offset = 0;
++
++ red->length = 8;
++ green->length = 8;
++ blue->length = 8;
++ break;
++ case 32:
++ red->offset = 0;
++ green->offset = 8;
++ blue->offset = 16;
++
++ red->length = 8;
++ green->length = 8;
++ blue->length = 8;
++ case 8: /* fall through */
++ default:
++ red->offset = green->offset = blue->offset = 0;
++ red->length = green->length = blue->length = bpp;
++ break;
++ }
++
++}
++
++
++static struct mq200_info* __init mq200_internal_init_fbinfo(void)
++{
++ struct mq200_info *info = NULL;
++
++ info = (struct mq200_info*)kmalloc(sizeof(*info), GFP_KERNEL);
++ if(!info)
++ return NULL;
++
++ /*
++ * Initialize memory
++ */
++ memset(info, 0, sizeof(struct mq200_info) );
++ spin_lock_init(&info->lock);
++
++ /* set the base IO addresses */
++ info->io_regions = MQ200_REGIONS;
++ info->monitor_info = MQ200_MONITOR;
++
++ info->fb_info.screen_base = (char *)info->io_regions.virt_fb_base;
++
++ /* fb_fix_screeninfo filling */
++ strcpy(info->fb_info.fix.id, "MQ200_FB" );
++ info->fb_info.fix.smem_start = info->io_regions.phys_fb_base;
++ info->fb_info.fix.smem_len = info->io_regions.fb_size; /* - CURSOR_IMAGE */
++ info->fb_info.fix.mmio_start = info->io_regions.phys_mmio_base;
++ info->fb_info.fix.mmio_len = MQ200_REGS_SIZE;
++ info->fb_info.fix.type = FB_TYPE_PACKED_PIXELS;
++ info->fb_info.fix.accel = FB_ACCEL_NONE;
++ info->fb_info.fix.line_length = MQ200_MONITOR_LINE_LENGTH(info);
++
++ if(MQ200_MONITOR_DEPTH(info) <= 8 )
++ info->fb_info.fix.visual = FB_VISUAL_PSEUDOCOLOR;
++ else if( MQ200_MONITOR_DEPTH(info) >= 16 )
++ info->fb_info.fix.visual = FB_VISUAL_DIRECTCOLOR;
++ else
++ panic("Calling mq200 with wrong display data\n");
++
++ /* set the variable screen info */
++ info->fb_info.var.xres = MQ200_MONITOR_HORI_RES(info);
++ info->fb_info.var.yres = MQ200_MONITOR_VERT_RES(info);
++ info->fb_info.var.xres_virtual = MQ200_MONITOR_HORI_RES(info);
++ info->fb_info.var.yres_virtual = MQ200_MONITOR_VERT_RES(info);
++ info->fb_info.var.bits_per_pixel = MQ200_MONITOR_DEPTH(info);
++
++ mq200_internal_init_color(&info->fb_info.var.red,
++ &info->fb_info.var.green,
++ &info->fb_info.var.blue,
++ MQ200_MONITOR_DEPTH(info) );
++
++ info->fb_info.var.transp.length = info->fb_info.var.transp.offset = 0;
++ info->fb_info.var.height = info->fb_info.var.width = -1;
++
++ info->fb_info.var.vmode = FB_VMODE_NONINTERLACED;
++ info->fb_info.var.pixclock = 10000;
++ info->fb_info.var.left_margin = info->fb_info.var.right_margin = 16;
++ info->fb_info.var.upper_margin = info->fb_info.var.lower_margin = 16;
++ info->fb_info.var.hsync_len = info->fb_info.var.vsync_len = 8;
++
++ info->fb_info.var.nonstd = 0;
++ info->fb_info.var.activate = FB_ACTIVATE_NOW;
++ info->fb_info.var.accel_flags = 0;
++
++ return info;
++}
++
++
++extern void mq200_register_attributes(struct device* );
++/*
++ * gets called from the bus
++ * we will register our framebuffer from here
++ */
++static int __init mq200_probe(struct device *dev)
++{
++ struct mq200_info *info = NULL;
++ int retv= 0;
++
++ info = mq200_internal_init_fbinfo();
++ if(!mq200_external_probe(info->io_regions.virt_mmio_base))
++ goto error_out;
++
++
++ GAFR &= ~(1<<3);
++ GPSR |= (1<<3);
++ GPDR |= (1<<3);
++
++ mq200_external_setqmode(&info->monitor_info,
++ info->io_regions.virt_mmio_base,
++ &info->lock);
++
++ info->fb_info.fbops = &mq200_ops;
++ info->fb_info.flags = FBINFO_FLAG_DEFAULT;
++
++ mq200_check_var(&info->fb_info.var, &info->fb_info );
++
++ fb_alloc_cmap(&info->fb_info.cmap, 1 << MQ200_MONITOR_DEPTH(info), 0 );
++
++ info->fb_info.pseudo_palette = (void*)info->pseudo_palette;
++
++ /* save the pointer to the mq200 struct in var */
++ info->fb_info.par = info;
++
++ retv = register_framebuffer(&info->fb_info );
++ if(retv < 0)
++ goto error_out;
++
++
++ /* will get unset if retv != 0 */
++ dev_set_drvdata(dev, info );
++ return retv;
++
++/*
++ * Free the info and exit
++ */
++error_out:
++ kfree(info);
++ return -EINVAL;
++}
++
++#ifdef CONFIG_PM
++static struct mq200_info* get_mq200_info( struct device *dev)
++{
++ return dev_get_drvdata(dev);
++}
++
++static unsigned long get_mmio_base( struct device *dev )
++{
++ struct mq200_info *info = get_mq200_info(dev);
++ return info->io_regions.virt_mmio_base;
++}
++
++static struct mq200_monitor_info* get_monitor_info( struct device *dev)
++{
++ struct mq200_info *info = get_mq200_info(dev);
++ return &info->monitor_info;
++}
++
++static spinlock_t* get_spinlock( struct device *dev)
++{
++ return &get_mq200_info(dev)->lock;
++}
++
++/*
++ * FIXME: make sure we only call mq200_external_offdisplay only once
++ * a 2nd time will hang the kernel -zecke
++ *
++ * FIXME: save the content of the framebuffer inside dev->saved_state
++ * so on resume we can memcpy it back into the buffer and userspace
++ * does not need to redraw
++ *
++ * functions for suspending and resuming
++ */
++static int mq200_suspend(struct device *dev, pm_message_t state)
++{
++
++ mq200_external_offdisplay( get_mmio_base(dev) );
++ clear_cs3_bit(DISPLAY_ON);
++
++
++ return 0;
++}
++
++static int mq200_resume(struct device *dev)
++{
++ unsigned long mem = get_mmio_base(dev);
++ struct mq200_monitor_info *monitor = get_monitor_info(dev);
++ mq200_external_setqmode(monitor, mem, get_spinlock(dev) );
++
++
++ /*
++ * Set display on if it was on
++ */
++ set_cs3_bit(DISPLAY_ON);
++
++ return 0;
++}
++
++
++#endif
++
++
++static struct device_driver mq200fb_driver = {
++ .name = "simpad-mq200",
++ .bus = &platform_bus_type,
++ .probe = mq200_probe, /* will be called after we've registered the driver */
++ .suspend = mq200_suspend,
++ .resume = mq200_resume
++};
++
++int __devinit mq200_init(void)
++{
++ return driver_register(&mq200fb_driver);
++}
++
++module_init(mq200_init);
++MODULE_DESCRIPTION("MQ200 framebuffer driver");
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Holger Hans Peter Freyther");
git.openpandora.org / openembedded.git / commitdiff