clk/qcom: apq8096: fix the sdhci clock

Select the right clock for sdhci.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250407175617.3494506-3-jorge.ramirez@oss.qualcomm.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>

diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index bc00826..551f52d 100644 (file)
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -83,7 +83,7 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
        struct msm_clk_priv *priv = dev_get_priv(clk->dev);
 
        switch (clk->id) {
-       case GCC_SDCC1_APPS_CLK: /* SDC1 */
+       case GCC_SDCC2_APPS_CLK: /* SDC2 */
                return clk_init_sdc(priv, rate);
                break;
        case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/