riscv: mbv: Align addresses with default DT
authorMichal Simek <michal.simek@amd.com>
Wed, 14 Feb 2024 11:52:29 +0000 (12:52 +0100)
committerMichal Simek <michal.simek@amd.com>
Fri, 1 Mar 2024 07:41:38 +0000 (08:41 +0100)
Better to align everything with memory map described in DT to avoid
mistakes. Execute both modes form the same address to make address map more
understandable.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/be54c668d5626ccd702507a86c2a95d1eaefc690.1707911544.git.michal.simek@amd.com
board/xilinx/mbv/Kconfig
configs/xilinx_mbv32_defconfig
configs/xilinx_mbv32_smode_defconfig

index 4bc9f72..553c232 100644 (file)
@@ -13,8 +13,7 @@ config SYS_CONFIG_NAME
        default "xilinx_mbv"
 
 config TEXT_BASE
-       default 0x80000000 if !RISCV_SMODE
-       default 0x80400000 if RISCV_SMODE && ARCH_RV32I
+       default 0x21200000
 
 config BOARD_SPECIFIC_OPTIONS
        def_bool y
index 2689495..912355f 100644 (file)
@@ -1,5 +1,4 @@
 CONFIG_RISCV=y
-CONFIG_TEXT_BASE=0x21200000
 CONFIG_SYS_MALLOC_LEN=0x800000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@@ -10,7 +9,7 @@ CONFIG_DEBUG_UART_BASE=0x40600000
 CONFIG_DEBUG_UART_CLOCK=1000000
 CONFIG_SYS_CLK_FREQ=100000000
 CONFIG_BOOT_SCRIPT_OFFSET=0x0
-CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_SYS_LOAD_ADDR=0x20200000
 CONFIG_DEBUG_UART=y
 CONFIG_TARGET_XILINX_MBV=y
 CONFIG_FIT=y
index c724d1b..3c91160 100644 (file)
@@ -1,5 +1,4 @@
 CONFIG_RISCV=y
-CONFIG_TEXT_BASE=0x21200000
 CONFIG_SYS_MALLOC_LEN=0x800000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@@ -10,7 +9,7 @@ CONFIG_DEBUG_UART_BASE=0x40600000
 CONFIG_DEBUG_UART_CLOCK=1000000
 CONFIG_SYS_CLK_FREQ=100000000
 CONFIG_BOOT_SCRIPT_OFFSET=0x0
-CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_SYS_LOAD_ADDR=0x20200000
 CONFIG_TARGET_XILINX_MBV=y
 CONFIG_RISCV_SMODE=y
 CONFIG_FIT=y