drm/i915: Don't enable IPS when pixel rate exceeds 95%
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 3 Jun 2015 12:45:11 +0000 (15:45 +0300)
committerJani Nikula <jani.nikula@intel.com>
Fri, 12 Jun 2015 10:14:33 +0000 (13:14 +0300)
Bspec says we shouldn't enable IPS on BDW when the pipe pixel rate
exceeds 95% of the core display clock. Apparently this can cause
underruns.

There's no similar restriction listed for HSW, so leave that one alone
for now.

v2: Add pipe_config_supports_ips() (Chris)
v3: Compare against the max cdclk insted of the current cdclk
v4: Rebased to the latest
v5: Rebased to the latest
v6: Fix for patch style problems

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83497
Tested-by: Timo Aaltonen <tjaalton@ubuntu.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_pm.c

index 445385d..c3f01aa 100644 (file)
@@ -6610,12 +6610,38 @@ retry:
        return ret;
 }
 
+static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
+                                    struct intel_crtc_state *pipe_config)
+{
+       if (pipe_config->pipe_bpp > 24)
+               return false;
+
+       /* HSW can handle pixel rate up to cdclk? */
+       if (IS_HASWELL(dev_priv->dev))
+               return true;
+
+       /*
+        * FIXME if we compare against max we should then
+        * increase the cdclk frequency when the current
+        * value is too low. The other option is to compare
+        * against the cdclk frequency we're going have post
+        * modeset (ie. one we computed using other constraints).
+        * Need to measure whether using a lower cdclk w/o IPS
+        * is better or worse than a higher cdclk w/ IPS.
+        */
+       return ilk_pipe_pixel_rate(pipe_config) <=
+               dev_priv->max_cdclk_freq * 95 / 100;
+}
+
 static void hsw_compute_ips_config(struct intel_crtc *crtc,
                                   struct intel_crtc_state *pipe_config)
 {
+       struct drm_device *dev = crtc->base.dev;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
        pipe_config->ips_enabled = i915.enable_ips &&
-                                  hsw_crtc_supports_ips(crtc) &&
-                                  pipe_config->pipe_bpp <= 24;
+               hsw_crtc_supports_ips(crtc) &&
+               pipe_config_supports_ips(dev_priv, pipe_config);
 }
 
 static int intel_crtc_compute_config(struct intel_crtc *crtc,
Simple merge
Simple merge