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sparc64: Add hypervisor interfaces for SPARC-T4 perf counter access.
authorDavid S. Miller <davem@davemloft.net>
Fri, 17 Aug 2012 03:35:41 +0000 (20:35 -0700)
committerDavid S. Miller <davem@davemloft.net>
Sun, 19 Aug 2012 06:03:53 +0000 (23:03 -0700)
Unlike for previous chips, access to the perf-counter control
registers are all hyper-privileged.  Therefore, access to them must go
through a hypervisor interface.

Signed-off-by: David S. Miller <davem@davemloft.net>

No differences found
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