clk: tegra30: Don't wait for PLL_U lock bit
authorTuomas Tynkkynen <ttynkkynen@nvidia.com>
Wed, 28 Aug 2013 15:18:47 +0000 (18:18 +0300)
committerMike Turquette <mturquette@linaro.org>
Thu, 29 Aug 2013 02:08:09 +0000 (19:08 -0700)
The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

No differences found