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clk: tegra: cclk_lp has a pllx/2 divider
authorAndrew Bresticker <abrestic@chromium.org>
Fri, 27 Dec 2013 00:44:26 +0000 (16:44 -0800)
committerPeter De Schrijver <pdeschrijver@nvidia.com>
Mon, 17 Feb 2014 14:18:28 +0000 (16:18 +0200)
When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines
whether cclk_lp output is divided by 2.  Set TEGRA_DIVIDER_2 so that
the clk_super driver is aware of this.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>

No differences found
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