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clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider
authorTomasz Figa <t.figa@samsung.com>
Fri, 20 Dec 2013 22:58:38 +0000 (07:58 +0900)
committerKukjin Kim <kgene.kim@samsung.com>
Fri, 20 Dec 2013 22:58:38 +0000 (07:58 +0900)
The clock was missing CLK_SET_RATE_PARENT flag, which caused rate
setting failures due to inability of reconfiguration of second
divider behind it.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

No differences found
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