linux-omap2 git: fix dispc init for beagleboard

diff --git a/packages/linux/linux-omap2-git/beagleboard/fix-dispc-clocks.patch b/packages/linux/linux-omap2-git/beagleboard/fix-dispc-clocks.patch
new file mode 100644 (file)
index 0000000..aade27f
--- /dev/null
+++ b/packages/linux/linux-omap2-git/beagleboard/fix-dispc-clocks.patch
@@ -0,0 +1,147 @@
+From linux-omap-owner@vger.kernel.org Sun Jun 22 10:11:39 2008\r
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+Date:  Sat, 21 Jun 2008 11:05:10 -0600 (MDT)\r
+From: Paul Walmsley <paul@pwsan.com>\r
+To: "Gadiyar, Anand" <gadiyar@ti.com>,\r
+        "linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>\r
+cc: Dirk Behme <dirk.behme@googlemail.com>,\r
+        "jouni.hogander@nokia.com" <jouni.hogander@nokia.com>\r
+Subject: [PATCH] OMAP3 clock: fix omap2_clk_wait_ready for OMAP3430ES2 DSS\r
+In-Reply-To: <5A47E75E594F054BAF48C5E4FC4B92AB022BB66209@dbde02.ent.ti.com>\r
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+\r
+\r
+On OMAP3430ES2, DSS has both an initiator standby CM_IDLEST bit, and a\r
+target idle CM_IDLEST bit.  This is a departure from previous silicon,\r
+which only had an initiator standby bit.\r
+\r
+This means we need to test the target idle bit after enabling\r
+dss1_alwon_fclk.  Previous clock code has done the wrong thing since ES2\r
+came out: it's either tested the wrong bit, causing intermittent\r
+\r
+    Clock dss1_alwon_fck didn't enable in 100000 tries\r
+\r
+messages; or not tested anything at all, causing intermittent crashes \r
+during DISPC initialization with:\r
+\r
+    Unhandled fault: external abort on non-linefetch (0x1028)\r
+\r
+This patch modifies omap2_clk_wait_ready() to wait for the DSS to become\r
+accessible after dss1_alwon_fclk is enabled.\r
+\r
+Thanks to Anand Gadiyar <gadiyar@ti.com> for identifying one of the\r
+problem patches.\r
+\r
+Signed-off-by: Paul Walmsley <paul@pwsan.com>\r
+---\r
+\r
+ arch/arm/mach-omap2/clock.c           |   30 ++++++++++++++++++++++++------\r
+ arch/arm/mach-omap2/cm-regbits-34xx.h |    4 +++-\r
+ 2 files changed, 27 insertions(+), 7 deletions(-)\r
+\r
+diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c\r
+index ed15868..1820f75 100644\r
+--- a/arch/arm/mach-omap2/clock.c\r
++++ b/arch/arm/mach-omap2/clock.c\r
+@@ -244,18 +244,36 @@ static void omap2_clk_wait_ready(struct clk *clk)\r
+       }\r
+ \r
+       /* REVISIT: What are the appropriate exclusions for 34XX? */\r
+-      /* OMAP3: ignore DSS-mod clocks */\r
+-      if (cpu_is_omap34xx() &&\r
+-          ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||\r
+-           (((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0)) &&\r
+-            clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))\r
+-              return;\r
++      if (cpu_is_omap34xx()) {\r
++\r
++              /* 3430ES1 DSS and SSI have no target idlest bits */\r
++              if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0) &&\r
++                  ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||\r
++                   ((reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(CORE_MOD, 0) &&\r
++                    clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))\r
++                      return;\r
++\r
++              /* Even for 3430ES2 DSS, only wait for dss1_alwon_fclk */\r
++              if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0) &&\r
++                  (reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&\r
++                  clk->enable_bit != OMAP3430_EN_DSS1_SHIFT)\r
++                      return;\r
++\r
++      }\r
+ \r
+       /* Check if both functional and interface clocks\r
+        * are running. */\r
+       bit = 1 << clk->enable_bit;\r
+       if (!(__raw_readl((__force void __iomem *)other_reg) & bit))\r
+               return;\r
++\r
++      /* OMAP3430ES2 DSS is an unusual case */\r
++      if (cpu_is_omap34xx() &&\r
++          (reg & ~0xff) == (__force u32)OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD, 0) &&\r
++          clk->enable_bit == OMAP3430_EN_DSS1_SHIFT) {\r
++              bit = OMAP3430ES2_ST_DSS_IDLE;\r
++      }\r
++\r
+       st_reg = ((other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */\r
+ \r
+       omap2_wait_clock_ready((__force void __iomem *)st_reg, bit, clk->name);\r
+diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h\r
+index 6ec66f4..946c552 100644\r
+--- a/arch/arm/mach-omap2/cm-regbits-34xx.h\r
++++ b/arch/arm/mach-omap2/cm-regbits-34xx.h\r
+@@ -500,7 +500,9 @@\r
+ #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT           0\r
+ \r
+ /* CM_IDLEST_DSS */\r
+-#define OMAP3430_ST_DSS                                       (1 << 0)\r
++#define OMAP3430ES2_ST_DSS_IDLE                               (1 << 1)\r
++#define OMAP3430ES2_ST_DSS_STDBY                      (1 << 0)\r
++#define OMAP3430ES1_ST_DSS                            (1 << 0)\r
+ \r
+ /* CM_AUTOIDLE_DSS */\r
+ #define OMAP3430_AUTO_DSS                             (1 << 0)\r
+--\r
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diff --git a/packages/linux/linux-omap2_git.bb b/packages/linux/linux-omap2_git.bb
index 90ccda5..252e3da 100644 (file)
--- a/packages/linux/linux-omap2_git.bb
+++ b/packages/linux/linux-omap2_git.bb
@@ -5,7 +5,7 @@ FILESDIR = "${@os.path.dirname(bb.data.getVar('FILE',d,1))}/linux-omap2-git/${MA
 SRCREV = "5b97d3ec6732c87741b2fc04f2956f097a458818"
 
 PV = "2.6.25+2.6.26-rc6+${PR}+git${SRCREV}"
-PR = "r26"
+PR = "r27"
 
 
 SRC_URI = "git://source.mvista.com/git/linux-omap-2.6.git;protocol=git \
@@ -20,6 +20,7 @@ SRC_URI_append_beagleboard = " file://no-harry-potter.diff;patch=1 \
            file://0001-omap3-cpuidle.patch;patch=1 \ 
            file://0002-omap3-cpuidle.patch;patch=1 \
            file://timer-suppression.patch;patch=1 \
+           file://fix-dispc-clocks.patch;patch=1 \
 "
 
 SRC_URI_append_omap3evm = " file://no-harry-potter.diff;patch=1 \