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ASoC: wm8960: Fix PLL register writes
authorMike Dyer <mike.dyer@md-soft.co.uk>
Fri, 16 Aug 2013 17:36:28 +0000 (18:36 +0100)
committerMark Brown <broonie@linaro.org>
Sun, 18 Aug 2013 15:30:26 +0000 (16:30 +0100)
Bit 9 of PLL2,3 and 4 is reserved as '0'. The 24bit fractional part
should be split across each register in 8bit chunks.

Signed-off-by: Mike Dyer <mike.dyer@md-soft.co.uk>
Signed-off-by: Mark Brown <broonie@linaro.org>
Cc: stable@vger.kernel.org

No differences found
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