sunxi: clock: H6: remove struct sunxi_prcm_reg

With the SPL clock code and the DRAM init routine we converted all users
of the H6 class "struct sunxi_prcm_reg" over to use #define'd register
offsets now.

Drop the whole definition of this struct now, since it's not needed
anymore, for all H6 and H616 boards.
This removes the entire fragile and questionable definition, and allows
new SoCs to share the code more easily.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
index 738cd68..d6653c3 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
@@ -9,7 +9,6 @@
 #define _SUN50I_PRCM_H
 
 #ifndef __ASSEMBLY__
-#include <linux/compiler.h>
 
 #define CCU_PRCM_I2C_GATE_RESET                0x19c
 #define CCU_PRCM_PLL_LDO_CFG           0x244
@@ -17,45 +16,6 @@
 #define CCU_PRCM_RES_CAL_CTRL          0x310
 #define CCU_PRCM_OHMS240               0x318
 
-struct sunxi_prcm_reg {
-       u32 cpus_cfg;           /* 0x000 */
-       u8 res0[0x8];           /* 0x004 */
-       u32 apbs1_cfg;          /* 0x00c */
-       u32 apbs2_cfg;          /* 0x010 */
-       u8 res1[0x108];         /* 0x014 */
-       u32 tmr_gate_reset;     /* 0x11c */
-       u8 res2[0xc];           /* 0x120 */
-       u32 twd_gate_reset;     /* 0x12c */
-       u8 res3[0xc];           /* 0x130 */
-       u32 pwm_gate_reset;     /* 0x13c */
-       u8 res4[0x4c];          /* 0x140 */
-       u32 uart_gate_reset;    /* 0x18c */
-       u8 res5[0xc];           /* 0x190 */
-       u32 twi_gate_reset;     /* 0x19c */
-       u8 res6[0x1c];          /* 0x1a0 */
-       u32 rsb_gate_reset;     /* 0x1bc */
-       u32 cir_cfg;            /* 0x1c0 */
-       u8 res7[0x8];           /* 0x1c4 */
-       u32 cir_gate_reset;     /* 0x1cc */
-       u8 res8[0x10];          /* 0x1d0 */
-       u32 w1_cfg;             /* 0x1e0 */
-       u8 res9[0x8];           /* 0x1e4 */
-       u32 w1_gate_reset;      /* 0x1ec */
-       u8 res10[0x1c];         /* 0x1f0 */
-       u32 rtc_gate_reset;     /* 0x20c */
-       u8 res11[0x34];         /* 0x210 */
-       u32 pll_ldo_cfg;        /* 0x244 */
-       u8 res12[0x8];          /* 0x248 */
-       u32 sys_pwroff_gating;  /* 0x250 */
-       u8 res13[0xbc];         /* 0x254 */
-       u32 res_cal_ctrl;       /* 0x310 */
-       u32 ohms200;            /* 0x314 */
-       u32 ohms240;            /* 0x318 */
-       u32 res_cal_status;     /* 0x31c */
-};
-check_member(sunxi_prcm_reg, rtc_gate_reset, 0x20c);
-check_member(sunxi_prcm_reg, res_cal_status, 0x31c);
-
 #define PRCM_TWI_GATE          (1 << 0)
 #define PRCM_TWI_RESET         (1 << 16)