TWL4030: use *_SIH_CTRL.COR bit to determine whether to read or write ISR to clear

TWL4030 interrupt status register bits can be cleared in one of two ways:
either by reading from the register, or by writing a 1 to the
appropriate bit(s) in the register.  This behavior can be altered at any
time by the <twlmodule>_SIH_CTRL.COR register bit ("clear-on-read").

The TWL4030 TRM is deeply confused as to whether COR=1 means that the
registers are cleared on reads, or cleared on writes.  Peter De
Schrijver <peter.de-schrijver> confirms that COR=1 means that the registers
are cleared on read.

So, for each TWL4030 SIH, check the value of the *_SIH_CTRL.COR bit, and if
it is 1, use reads to clear the ISRs; if it is 0, use writes.

Also, use WARN_ON() to warn if the read/write failed, and don't skip
the rest of the initialization on failure either.

Thanks to Peter for his help with this patch.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>