MIPS: Emulate the new MIPS R6 branch compact (BC) instruction

MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 19d3bc1..9ce5e34 100644 (file)
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -31,7 +31,7 @@ enum major_op {
        lbu_op, lhu_op, lwr_op, lwu_op,
        sb_op, sh_op, swl_op, sw_op,
        sdl_op, sdr_op, swr_op, cache_op,
-       ll_op, lwc1_op, lwc2_op, pref_op,
+       ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
        lld_op, ldc1_op, ldc2_op, ld_op,
        sc_op, swc1_op, swc2_op, major_3b_op,
        scd_op, sdc1_op, sdc2_op, sd_op

diff --cc arch/mips/kernel/branch.c
Simple merge

diff --cc arch/mips/math-emu/cp1emu.c
Simple merge