[ARM] Feroceon: L1 cache range operation support
authorStanislav Samsonov <samsonov@marvell.com>
Tue, 3 Jun 2008 08:24:40 +0000 (11:24 +0300)
committerLennert Buytenhek <buytenh@marvell.com>
Sun, 22 Jun 2008 20:45:03 +0000 (22:45 +0200)
This patch adds support for the L1 D cache range operations that
are supported by the Marvell Discovery Duo and Marvell Kirkwood
ARM SoCs.

Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Acked-by: Saeed Bishara <saeed@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

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