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CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck
authorPeter Ujfalusi <peter.ujfalusi@ti.com>
Wed, 30 Apr 2014 11:39:37 +0000 (14:39 +0300)
committerTero Kristo <t-kristo@ti.com>
Fri, 6 Jun 2014 17:33:34 +0000 (20:33 +0300)
In order to get correct clock dividers for AESS/ABE we need to set the
dpll_abe_m2x2_ck rate to be double of dpll_abe_ck.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

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