SPEAr : Adding basic SPEAr architecture support.
authorVipin KUMAR <vipin.kumar@st.com>
Fri, 15 Jan 2010 13:45:43 +0000 (19:15 +0530)
committerTom Rix <Tom.Rix@windriver.com>
Sat, 23 Jan 2010 14:15:49 +0000 (08:15 -0600)
SPEAr Architecture support added. It contains the support for
following SPEAr blocks
- Timer
- System controller
- Misc registers

Signed-off-by: Vipin <vipin.kumar@st.com>
cpu/arm926ejs/spear/Makefile [new file with mode: 0755]
cpu/arm926ejs/spear/reset.c [new file with mode: 0755]
cpu/arm926ejs/spear/timer.c [new file with mode: 0755]
include/asm-arm/arch-spear/hardware.h [new file with mode: 0644]
include/asm-arm/arch-spear/spr_gpt.h [new file with mode: 0755]
include/asm-arm/arch-spear/spr_misc.h [new file with mode: 0644]
include/asm-arm/arch-spear/spr_syscntl.h [new file with mode: 0644]

diff --git a/cpu/arm926ejs/spear/Makefile b/cpu/arm926ejs/spear/Makefile
new file mode 100755 (executable)
index 0000000..bf8dfa8
--- /dev/null
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(SOC).a
+
+COBJS  := reset.o \
+          timer.o
+SOBJS  :=
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm926ejs/spear/reset.c b/cpu/arm926ejs/spear/reset.c
new file mode 100755 (executable)
index 0000000..73ad86d
--- /dev/null
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_syscntl.h>
+
+void reset_cpu(ulong ignored)
+{
+       struct syscntl_regs *syscntl_regs_p =
+           (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
+
+       printf("System is going to reboot ...\n");
+
+       /*
+        * This 1 second delay will allow the above message
+        * to be printed before reset
+        */
+       udelay((1000 * 1000));
+
+       /* Going into slow mode before resetting SOC */
+       writel(0x02, &syscntl_regs_p->scctrl);
+
+       /*
+        * Writing any value to the system status register will
+        * reset the SoC
+        */
+       writel(0x00, &syscntl_regs_p->scsysstat);
+
+       /* system will restart */
+       while (1)
+               ;
+}
diff --git a/cpu/arm926ejs/spear/timer.c b/cpu/arm926ejs/spear/timer.c
new file mode 100755 (executable)
index 0000000..06858b4
--- /dev/null
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_gpt.h>
+#include <asm/arch/spr_misc.h>
+
+#define GPT_RESOLUTION (CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ)
+#define READ_TIMER()   (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
+
+static struct gpt_regs *const gpt_regs_p =
+    (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE;
+
+static struct misc_regs *const misc_regs_p =
+    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+       u32 synth;
+
+       /* Prescaler setting */
+#if defined(CONFIG_SPEAR3XX)
+       writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg);
+       synth = MISC_GPT4SYNTH;
+#elif defined(CONFIG_SPEAR600)
+       writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
+       synth = MISC_GPT3SYNTH;
+#else
+# error Incorrect config. Can only be spear{600|300|310|320}
+#endif
+
+       writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
+              &misc_regs_p->periph_clk_cfg);
+
+       /* disable timers */
+       writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control);
+
+       /* load value for free running */
+       writel(GPT_FREE_RUNNING, &gpt_regs_p->compare);
+
+       /* auto reload, start timer */
+       writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control);
+
+       reset_timer_masked();
+
+       return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+       reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+       return (get_timer_masked() / GPT_RESOLUTION) - base;
+}
+
+void set_timer(ulong t)
+{
+       timestamp = t;
+}
+
+void __udelay(unsigned long usec)
+{
+       ulong tmo;
+       ulong start = get_timer_masked();
+       ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100);
+       ulong rndoff;
+
+       rndoff = (usec % 10) ? 1 : 0;
+
+       /* tenudelcnt timer tick gives 10 microsecconds delay */
+       tmo = ((usec / 10) + rndoff) * tenudelcnt;
+
+       while ((ulong) (get_timer_masked() - start) < tmo)
+               ;
+}
+
+void reset_timer_masked(void)
+{
+       /* reset time */
+       lastdec = READ_TIMER();
+       timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+       ulong now = READ_TIMER();
+
+       if (now >= lastdec) {
+               /* normal mode */
+               timestamp += now - lastdec;
+       } else {
+               /* we have an overflow ... */
+               timestamp += now + GPT_FREE_RUNNING - lastdec;
+       }
+       lastdec = now;
+
+       return timestamp;
+}
+
+void udelay_masked(unsigned long usec)
+{
+       return udelay(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+       return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+       return CONFIG_SPEAR_HZ;
+}
diff --git a/include/asm-arm/arch-spear/hardware.h b/include/asm-arm/arch-spear/hardware.h
new file mode 100644 (file)
index 0000000..818f36c
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define CONFIG_SYS_USBD_BASE                   (0xE1100000)
+#define CONFIG_SYS_PLUG_BASE                   (0xE1200000)
+#define CONFIG_SYS_FIFO_BASE                   (0xE1000800)
+#define CONFIG_SYS_SMI_BASE                    (0xFC000000)
+#define CONFIG_SPEAR_SYSCNTLBASE               (0xFCA00000)
+#define CONFIG_SPEAR_TIMERBASE                 (0xFC800000)
+#define CONFIG_SPEAR_MISCBASE                  (0xFCA80000)
+
+#define CONFIG_SYS_NAND_CLE                    (1 << 16)
+#define CONFIG_SYS_NAND_ALE                    (1 << 17)
+
+#if defined(CONFIG_SPEAR600)
+#define CONFIG_SYS_I2C_BASE                    (0xD0200000)
+#define CONFIG_SPEAR_FSMCBASE                  (0xD1800000)
+
+#elif defined(CONFIG_SPEAR300)
+#define CONFIG_SYS_I2C_BASE                    (0xD0180000)
+#define CONFIG_SPEAR_FSMCBASE                  (0x94000000)
+
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_I2C_BASE                    (0xD0180000)
+#define CONFIG_SPEAR_FSMCBASE                  (0x44000000)
+
+#undef CONFIG_SYS_NAND_CLE
+#undef CONFIG_SYS_NAND_ALE
+#define CONFIG_SYS_NAND_CLE                    (1 << 17)
+#define CONFIG_SYS_NAND_ALE                    (1 << 16)
+
+#define CONFIG_SPEAR_EMIBASE                   (0x4F000000)
+#define CONFIG_SPEAR_RASBASE                   (0xB4000000)
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_I2C_BASE                    (0xD0180000)
+#define CONFIG_SPEAR_FSMCBASE                  (0x4C000000)
+
+#define CONFIG_SPEAR_EMIBASE                   (0x40000000)
+#define CONFIG_SPEAR_RASBASE                   (0xB3000000)
+
+#endif
+#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-spear/spr_gpt.h b/include/asm-arm/arch-spear/spr_gpt.h
new file mode 100755 (executable)
index 0000000..965b5ab
--- /dev/null
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPR_GPT_H
+#define _SPR_GPT_H
+
+struct gpt_regs {
+       u8 reserved[0x80];
+       u32 control;
+       u32 status;
+       u32 compare;
+       u32 count;
+       u32 capture_re;
+       u32 capture_fe;
+};
+
+/*
+ * TIMER_CONTROL register settings
+ */
+
+#define GPT_PRESCALER_MASK             0x000F
+#define GPT_PRESCALER_1                        0x0000
+#define GPT_PRESCALER_2                0x0001
+#define GPT_PRESCALER_4                0x0002
+#define GPT_PRESCALER_8                0x0003
+#define GPT_PRESCALER_16               0x0004
+#define GPT_PRESCALER_32               0x0005
+#define GPT_PRESCALER_64               0x0006
+#define GPT_PRESCALER_128              0x0007
+#define GPT_PRESCALER_256              0x0008
+
+#define GPT_MODE_SINGLE_SHOT           0x0010
+#define GPT_MODE_AUTO_RELOAD           0x0000
+
+#define GPT_ENABLE                     0x0020
+
+#define GPT_CAPT_MODE_MASK             0x00C0
+#define GPT_CAPT_MODE_NONE             0x0000
+#define GPT_CAPT_MODE_RE               0x0040
+#define GPT_CAPT_MODE_FE               0x0080
+#define GPT_CAPT_MODE_BOTH             0x00C0
+
+#define GPT_INT_MATCH                  0x0100
+#define GPT_INT_FE                     0x0200
+#define GPT_INT_RE                     0x0400
+
+/*
+ * TIMER_STATUS register settings
+ */
+
+#define GPT_STS_MATCH                  0x0001
+#define GPT_STS_FE                     0x0002
+#define GPT_STS_RE                     0x0004
+
+/*
+ * TIMER_COMPARE register settings
+ */
+
+#define GPT_FREE_RUNNING               0xFFFF
+
+/* Timer, HZ specific defines */
+#define CONFIG_SPEAR_HZ                        (1000)
+#define CONFIG_SPEAR_HZ_CLOCK          (8300000)
+
+#endif
diff --git a/include/asm-arm/arch-spear/spr_misc.h b/include/asm-arm/arch-spear/spr_misc.h
new file mode 100644 (file)
index 0000000..8b96d9b
--- /dev/null
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPR_MISC_H
+#define _SPR_MISC_H
+
+struct misc_regs {
+       u32 auto_cfg_reg;       /* 0x0 */
+       u32 armdbg_ctr_reg;     /* 0x4 */
+       u32 pll1_cntl;          /* 0x8 */
+       u32 pll1_frq;           /* 0xc */
+       u32 pll1_mod;           /* 0x10 */
+       u32 pll2_cntl;          /* 0x14 */
+       u32 pll2_frq;           /* 0x18 */
+       u32 pll2_mod;           /* 0x1C */
+       u32 pll_ctr_reg;        /* 0x20 */
+       u32 amba_clk_cfg;       /* 0x24 */
+       u32 periph_clk_cfg;     /* 0x28 */
+       u32 periph1_clken;      /* 0x2C */
+       u32 periph2_clken;      /* 0x30 */
+       u32 ras_clken;          /* 0x34 */
+       u32 periph1_rst;        /* 0x38 */
+       u32 periph2_rst;        /* 0x3C */
+       u32 ras_rst;            /* 0x40 */
+       u32 prsc1_clk_cfg;      /* 0x44 */
+       u32 prsc2_clk_cfg;      /* 0x48 */
+       u32 prsc3_clk_cfg;      /* 0x4C */
+       u32 amem_cfg_ctrl;      /* 0x50 */
+       u32 port_cfg_ctrl;      /* 0x54 */
+       u32 reserved_1;         /* 0x58 */
+       u32 clcd_synth_clk;     /* 0x5C */
+       u32 irda_synth_clk;     /* 0x60 */
+       u32 uart_synth_clk;     /* 0x64 */
+       u32 gmac_synth_clk;     /* 0x68 */
+       u32 ras_synth1_clk;     /* 0x6C */
+       u32 ras_synth2_clk;     /* 0x70 */
+       u32 ras_synth3_clk;     /* 0x74 */
+       u32 ras_synth4_clk;     /* 0x78 */
+       u32 arb_icm_ml1;        /* 0x7C */
+       u32 arb_icm_ml2;        /* 0x80 */
+       u32 arb_icm_ml3;        /* 0x84 */
+       u32 arb_icm_ml4;        /* 0x88 */
+       u32 arb_icm_ml5;        /* 0x8C */
+       u32 arb_icm_ml6;        /* 0x90 */
+       u32 arb_icm_ml7;        /* 0x94 */
+       u32 arb_icm_ml8;        /* 0x98 */
+       u32 arb_icm_ml9;        /* 0x9C */
+       u32 dma_src_sel;        /* 0xA0 */
+       u32 uphy_ctr_reg;       /* 0xA4 */
+       u32 gmac_ctr_reg;       /* 0xA8 */
+       u32 port_bridge_ctrl;   /* 0xAC */
+       u32 reserved_2[4];      /* 0xB0--0xBC */
+       u32 prc1_ilck_ctrl_reg; /* 0xC0 */
+       u32 prc2_ilck_ctrl_reg; /* 0xC4 */
+       u32 prc3_ilck_ctrl_reg; /* 0xC8 */
+       u32 prc4_ilck_ctrl_reg; /* 0xCC */
+       u32 prc1_intr_ctrl_reg; /* 0xD0 */
+       u32 prc2_intr_ctrl_reg; /* 0xD4 */
+       u32 prc3_intr_ctrl_reg; /* 0xD8 */
+       u32 prc4_intr_ctrl_reg; /* 0xDC */
+       u32 powerdown_cfg_reg;  /* 0xE0 */
+       u32 ddr_1v8_compensation;       /* 0xE4  */
+       u32 ddr_2v5_compensation;       /* 0xE8 */
+       u32 core_3v3_compensation;      /* 0xEC */
+       u32 ddr_pad;            /* 0xF0 */
+       u32 bist1_ctr_reg;      /* 0xF4 */
+       u32 bist2_ctr_reg;      /* 0xF8 */
+       u32 bist3_ctr_reg;      /* 0xFC */
+       u32 bist4_ctr_reg;      /* 0x100 */
+       u32 bist5_ctr_reg;      /* 0x104 */
+       u32 bist1_rslt_reg;     /* 0x108 */
+       u32 bist2_rslt_reg;     /* 0x10C */
+       u32 bist3_rslt_reg;     /* 0x110 */
+       u32 bist4_rslt_reg;     /* 0x114 */
+       u32 bist5_rslt_reg;     /* 0x118 */
+       u32 syst_error_reg;     /* 0x11C */
+       u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */
+       u32 ras_gpp1_in;        /* 0x8000 */
+       u32 ras_gpp2_in;        /* 0x8004 */
+       u32 ras_gpp1_out;       /* 0x8008 */
+       u32 ras_gpp2_out;       /* 0x800C */
+};
+
+/* AUTO_CFG_REG value */
+#define MISC_SOCCFGMSK                  0x0000003F
+#define MISC_SOCCFG30                   0x0000000C
+#define MISC_SOCCFG31                   0x0000000D
+#define MISC_NANDDIS                   0x00020000
+
+/* PERIPH_CLK_CFG value */
+#define MISC_GPT3SYNTH                 0x00000400
+#define MISC_GPT4SYNTH                 0x00000800
+
+/* PRSC_CLK_CFG value */
+/*
+ * Fout = Fin / (2^(N+1) * (M + 1))
+ */
+#define MISC_PRSC_N_1                  0x00001000
+#define MISC_PRSC_M_9                  0x00000009
+#define MISC_PRSC_N_4                  0x00004000
+#define MISC_PRSC_M_399                        0x0000018F
+#define MISC_PRSC_N_6                  0x00006000
+#define MISC_PRSC_M_2593               0x00000A21
+#define MISC_PRSC_M_124                        0x0000007C
+#define MISC_PRSC_CFG                  (MISC_PRSC_N_1 | MISC_PRSC_M_9)
+
+/* PERIPH1_CLKEN, PERIPH1_RST value */
+#define MISC_USBDENB                   0x01000000
+
+#endif
diff --git a/include/asm-arm/arch-spear/spr_syscntl.h b/include/asm-arm/arch-spear/spr_syscntl.h
new file mode 100644 (file)
index 0000000..3c92f09
--- /dev/null
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2009
+ * Ryan CHEN, ST Micoelectronics, ryan.chen@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+struct syscntl_regs {
+       u32 scctrl;
+       u32 scsysstat;
+       u32 scimctrl;
+       u32 scimsysstat;
+       u32 scxtalctrl;
+       u32 scpllctrl;
+       u32 scpllfctrl;
+       u32 scperctrl0;
+       u32 scperctrl1;
+       u32 scperen;
+       u32 scperdis;
+       const u32 scperclken;
+       const u32 scperstat;
+};