clk/qcom: sdm845: add support for sdm670

The global clock controller on SDM670 is similar to SDM845, so let's add
support here.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: David Wronek <david.wronek@mainlining.org>
Link: https://lore.kernel.org/r/20251003-sdm670-v2-2-52c0fa481286@mainlining.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>

diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index 5c8702e..c9a057c 100644 (file)
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -23,6 +23,7 @@
 #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018
 #define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf030
 #define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf05c
+#define SDCC1_APPS_CLK_CMD_RCGR 0x26028
 #define SDCC2_APPS_CLK_CMD_RCGR 0x1400c
 
 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
@@ -44,6 +45,18 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
        { }
 };
 
+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
+       F(144000, CFG_CLK_SRC_CXO, 16, 3, 25),
+       F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
+       F(20000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 1, 3),
+       F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 1, 2),
+       F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
+       F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+       F(192000000, CFG_CLK_SRC_GPLL6, 2, 0, 0),
+       F(384000000, CFG_CLK_SRC_GPLL6, 1, 0, 0),
+       { }
+};
+
 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
        F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
        F(9600000, CFG_CLK_SRC_CXO, 2, 0, 0),
@@ -55,6 +68,22 @@ static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
        { }
 };
 
+static ulong sdm670_clk_set_rate(struct clk *clk, ulong rate)
+{
+       struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+       const struct freq_tbl *freq;
+
+       switch (clk->id) {
+       case GCC_SDCC1_APPS_CLK:
+               freq = qcom_find_freq(ftbl_gcc_sdcc1_apps_clk_src, rate);
+               clk_rcg_set_rate_mnd(priv->base, SDCC1_APPS_CLK_CMD_RCGR,
+                                    freq->pre_div, freq->m, freq->n, freq->src, 8);
+               return freq->freq;
+       default:
+               return 0;
+       }
+}
+
 static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate)
 {
        struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -76,6 +105,54 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate)
        }
 }
 
+static const struct gate_clk sdm670_clks[] = {
+       GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK,           0x8201c, 0x00000001),
+       GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK,         0x0502c, 0x00000001),
+       GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK,                0x5200c, 0x00000400),
+       GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK,                0x5200c, 0x00000800),
+       GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK,                0x5200c, 0x00001000),
+       GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK,                0x5200c, 0x00002000),
+       GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK,                0x5200c, 0x00004000),
+       GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK,                0x5200c, 0x00008000),
+       GATE_CLK(GCC_QUPV3_WRAP0_S6_CLK,                0x5200c, 0x00010000),
+       GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK,                0x5200c, 0x00020000),
+       GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK,                0x5200c, 0x00400000),
+       GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK,                0x5200c, 0x00800000),
+       GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK,                0x5200c, 0x02000000),
+       GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK,                0x5200c, 0x04000000),
+       GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK,                0x5200c, 0x08000000),
+       GATE_CLK(GCC_QUPV3_WRAP1_S6_CLK,                0x5200c, 0x10000000),
+       GATE_CLK(GCC_QUPV3_WRAP1_S7_CLK,                0x5200c, 0x20000000),
+       GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK,            0x5200c, 0x00000040),
+       GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK,            0x5200c, 0x00000080),
+       GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK,            0x5200c, 0x00100000),
+       GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK,            0x5200c, 0x00200000),
+       GATE_CLK(GCC_SDCC1_AHB_CLK,                     0x26008, 0x00000001),
+       GATE_CLK(GCC_SDCC1_APPS_CLK,                    0x26004, 0x00000001),
+       GATE_CLK(GCC_SDCC1_ICE_CORE_CLK,                0x2600c, 0x00000001),
+       GATE_CLK(GCC_SDCC2_AHB_CLK,                     0x14008, 0x00000001),
+       GATE_CLK(GCC_SDCC2_APPS_CLK,                    0x14004, 0x00000001),
+       GATE_CLK(GCC_SDCC4_AHB_CLK,                     0x16008, 0x00000001),
+       GATE_CLK(GCC_SDCC4_APPS_CLK,                    0x16004, 0x00000001),
+       GATE_CLK(GCC_UFS_MEM_CLKREF_CLK,                0x8c000, 0x00000001),
+       GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK,             0x82024, 0x00000001),
+       GATE_CLK(GCC_UFS_PHY_AHB_CLK,                   0x77010, 0x00000001),
+       GATE_CLK(GCC_UFS_PHY_AXI_CLK,                   0x7700c, 0x00000001),
+       GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK,              0x77058, 0x00000001),
+       GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK,               0x7708c, 0x00000001),
+       GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK,           0x77018, 0x00000001),
+       GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK,           0x77014, 0x00000001),
+       GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK,           0x77054, 0x00000001),
+       GATE_CLK(GCC_USB30_PRIM_MASTER_CLK,             0x0f00c, 0x00000001),
+       GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK,          0x0f014, 0x00000001),
+       GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK,              0x0f010, 0x00000001),
+       GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK,              0x8c008, 0x00000001),
+       GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK,             0x0f04c, 0x00000001),
+       GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK,         0x0f050, 0x00000001),
+       GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK,            0x0f054, 0x00000001),
+       GATE_CLK(GCC_USB_PHY_CFG_AHB2PHY_CLK,           0x6a004, 0x00000001),
+};
+
 static const struct gate_clk sdm845_clks[] = {
        GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK,           0x8201c, 0x00000001),
        GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK,            0x82020, 0x00000001),
@@ -140,6 +217,28 @@ static const struct gate_clk sdm845_clks[] = {
        GATE_CLK(GCC_USB_PHY_CFG_AHB2PHY_CLK,           0x6a004, 0x00000001),
 };
 
+static int sdm670_clk_enable(struct clk *clk)
+{
+       struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+       debug("%s: clk %s\n", __func__, sdm670_clks[clk->id].name);
+
+       switch (clk->id) {
+       case GCC_USB30_PRIM_MASTER_CLK:
+               qcom_gate_clk_en(priv, GCC_USB_PHY_CFG_AHB2PHY_CLK);
+               /* These numbers are just pulled from the frequency tables in the Linux driver */
+               clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
+                                    (4.5 * 2) - 1, 0, 0, 1 << 8, 8);
+               clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR,
+                                    1, 0, 0, 0, 8);
+               clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR,
+                                    1, 0, 0, 0, 8);
+               break;
+       }
+
+       return qcom_gate_clk_en(priv, clk->id);
+}
+
 static int sdm845_clk_enable(struct clk *clk)
 {
        struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -188,6 +287,17 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = {
        [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
 };
 
+static const struct qcom_power_map sdm670_gdscs[] = {
+       [UFS_PHY_GDSC] = { 0x77004 },
+       [USB30_PRIM_GDSC] = { 0xf004 },
+       [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 },
+       [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 },
+       [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 },
+       [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 },
+       [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 },
+       [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 },
+};
+
 static const struct qcom_power_map sdm845_gdscs[] = {
        [PCIE_0_GDSC] = { 0x6b004 },
        [PCIE_1_GDSC] = { 0x8d004 },
@@ -292,6 +402,19 @@ static const char *const sdm845_rcg_names[] = {
        "GCC_UFS_PHY_PHY_AUX",
 };
 
+static struct msm_clk_data sdm670_clk_data = {
+       /* Snapdragon 670 can function without its own exclusive resets. */
+       .resets = sdm845_gcc_resets,
+       .num_resets = ARRAY_SIZE(sdm845_gcc_resets),
+       .clks = sdm670_clks,
+       .num_clks = ARRAY_SIZE(sdm670_clks),
+       .power_domains = sdm670_gdscs,
+       .num_power_domains = ARRAY_SIZE(sdm670_gdscs),
+
+       .enable = sdm670_clk_enable,
+       .set_rate = sdm670_clk_set_rate,
+};
+
 static struct msm_clk_data sdm845_clk_data = {
        .resets = sdm845_gcc_resets,
        .num_resets = ARRAY_SIZE(sdm845_gcc_resets),
@@ -310,6 +433,10 @@ static struct msm_clk_data sdm845_clk_data = {
 };
 
 static const struct udevice_id gcc_sdm845_of_match[] = {
+       {
+               .compatible = "qcom,gcc-sdm670",
+               .data = (ulong)&sdm670_clk_data,
+       },
        {
                .compatible = "qcom,gcc-sdm845",
                .data = (ulong)&sdm845_clk_data,