omap2 clock: use standard clk->enable/disable for APLLs

Now that we're calling the clock-specific enable & disable code, we can
get rid of the special-case code in _omap2_clk_{enable,disable}() for the
APLLs.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index f389e9d..80fcd7f 100644 (file)
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -213,7 +213,7 @@ static int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name)
 
 
 /* Enable an APLL if off */
-static void omap2_clk_fixed_enable(struct clk *clk)
+static int omap2_clk_fixed_enable(struct clk *clk)
 {
        u32 cval, apll_mask;
 
@@ -222,7 +222,7 @@ static void omap2_clk_fixed_enable(struct clk *clk)
        cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 
        if ((cval & apll_mask) == apll_mask)
-               return;   /* apll already enabled */
+               return 0;   /* apll already enabled */
 
        cval &= ~apll_mask;
        cval |= apll_mask;
@@ -235,6 +235,12 @@ static void omap2_clk_fixed_enable(struct clk *clk)
 
        omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
                            clk->name);
+
+       /*
+        * REVISIT: Should we return an error code if omap2_wait_clock_ready()
+        * fails?
+        */
+       return 0;
 }
 
 static void omap2_clk_wait_ready(struct clk *clk)
@@ -289,11 +295,6 @@ static int _omap2_clk_enable(struct clk * clk)
                return -EINVAL;
        }
 
-       if (clk->enable_reg == OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
-               omap2_clk_fixed_enable(clk);
-               return 0;
-       }
-
        regval32 = cm_read_reg(clk->enable_reg);
        regval32 |= (1 << clk->enable_bit);
        cm_write_reg(regval32, clk->enable_reg);
@@ -337,11 +338,6 @@ static void _omap2_clk_disable(struct clk *clk)
                return;
        }
 
-       if (clk->enable_reg == OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN)) {
-               omap2_clk_fixed_disable(clk);
-               return;
-       }
-
        regval32 = cm_read_reg(clk->enable_reg);
        regval32 &= ~(1 << clk->enable_bit);
        cm_write_reg(regval32, clk->enable_reg);

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index bd64fba..4b2ab96 100644 (file)
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -38,6 +38,8 @@ static u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
 static u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
 static void omap2_dpll_recalc(struct clk *clk);
 static void omap2_fixed_divisor_recalc(struct clk *clk);
+static int omap2_clk_fixed_enable(struct clk *clk);
+static void omap2_clk_fixed_disable(struct clk *clk);
 static long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 static int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate);
@@ -647,6 +649,8 @@ static struct clk apll96_ck = {
                                RATE_FIXED | RATE_PROPAGATES,
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
+       .enable         = &omap2_clk_fixed_enable,
+       .disable        = &omap2_clk_fixed_disable,
        .recalc         = &propagate_rate,
 };
 
@@ -658,6 +662,8 @@ static struct clk apll54_ck = {
                                RATE_FIXED | RATE_PROPAGATES,
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
+       .enable         = &omap2_clk_fixed_enable,
+       .disable        = &omap2_clk_fixed_disable,
        .recalc         = &propagate_rate,
 };