#export KERNELDIR = /opt/oe/stuff/build/tmp/work/beagleboard-angstrom-linux-gnueabi/linux-omap-2.6.29-r44/git/
export TI_PLATFORM ?= omap3
+SUPPORT_ANDROID_PLATFORM ?= 1
export KERNEL_PATH=$(KERNELDIR)
export KERNEL_SRC=$(KERNELDIR)
SYS_CFLAGS.$(SUPPORT_SGX_EDM_MEMORY_DEBUG) += -DSUPPORT_SGX_EDM_MEMORY_DEBUG
-SYS_CFLAGS.$(SUPPORT_ANDROID_PLATFORM) += -DSUPPORT_ANDROID_PLATFORM
+SYS_CFLAGS.$(SUPPORT_ANDROID_PLATFORM) += -DSUPPORT_ANDROID_PLATFORM -DANDROID
SYS_CFLAGS.$(SUPPORT_GRAPHICS_HAL) += -DSUPPORT_GRAPHICS_HAL
SYS_CFLAGS.$(SUPPORT_GRAPHICS_HAL) += -DGRALLOC_VARIANT="\"$(GRALLOC_VARIANT)\""
ifeq ($(PDUMP),1)
+ifneq ($(SUPPORT_DRI_DRM),1)
PDUMP_SUBDIRS += $(EURASIAROOT)/tools/intern/debug/dbgdriv/linux
endif
+endif
KBUILD_SUBDIRS = \
$(PDUMP_SUBDIRS) \
#
#
+PVR_KBUILD_IN_KERNEL ?= 0
+PVR_KBUILD_MODULE_MAKEFILE ?= Makefile
+
+ifeq ($(PVR_KBUILD_IN_KERNEL),1)
+# If cross compile is not set, then set it to null to prevent it being
+# set by the platform specific make files.
+CROSS_COMPILE ?=
+endif
+
# Include target specific variables.
#
include $(EURASIAROOT)/eurasiacon/build/linux/$(PVR_BUILD_DIR)/makefile.shared_conf
# Include the local module settings.
#
-include Makefile
+include $(PVR_KBUILD_MODULE_MAKEFILE)
+ifneq ($(PVR_KBUILD_IN_KERNEL),1)
# Include the build rules for kbuild modules
#
include $(EURASIAROOT)/eurasiacon/build/linux/kbuild/Makefile.kbuild_subdir_rules
-
+endif
#
#
-obj-m = $(MODULE).o
+PVR_KBUILD_CONFIG_FLAG ?= m
+ifneq ($(PVR_KBUILD_IN_KERNEL),1)
+obj-$(PVR_KBUILD_CONFIG_FLAG) =
+endif
+
+obj-$(PVR_KBUILD_CONFIG_FLAG) += $(MODULE).o
$(MODULE)-objs = $(SOURCES:.c=.o)
EXTRA_CFLAGS = $(INCLUDES) \
$(ALL_CFLAGS_kbuild) \
- -Wall -fno-strict-aliasing -Werror
+ -Wall -fno-strict-aliasing
+ifneq ($(PVR_KBUILD_IN_KERNEL),1)
+ifneq ($(SUPPORT_DRI_DRM_EXT),1)
+ EXTRA_CFLAGS += -Werror
+endif
+endif
+
+ifneq ($(PVR_KBUILD_IN_KERNEL),1)
ifeq ($(SILENT),@)
KBUILD_VERBOSE ?= 0
else
KBUILD_VERBOSE ?= 1
endif
-
+endif
STRIP = $(CROSS_COMPILE)strip
SIZE = $(CROSS_COMPILE)size
-ifdef QAC_ANALYSE
-CC=perl $(ANALROOT)/wrapper.pl -wcf $(ANALROOT)/eurasia_linux.cfg $(CROSS_COMPILE)gcc
-else
CC= $(CROSS_COMPILE)gcc
+ifdef QAC_ANALYSE
+ifneq ("$(CROSS_COMPILE)","")
+CC= perl "$(ANALROOT)/wrapper.pl -wcf $(ANALROOT)/eurasia_linux.cfg $(CROSS_COMPILE)gcc"
+endif
endif
CAT ?= cat
-DPVR_BUILD_TYPE="\"$(BUILD)\""
# Don't support HW recovery on debug builds
-CBUILD.debug = -DDEBUG
+CBUILD.debug = -DDEBUG_PVR
CBUILD.timing = -DTIMING
CBUILD.release = -DRELEASE
CFLAGS.debug = -g -O0 -DDLL_METRIC=1
CFLAGS.timing = $(OPTIM) -g -DDLL_METRIC=1 -DTIMING
CFLAGS.release = $(OPTIM) -g
-CFLAGS = $(CFLAGS.$(BUILD))
# Defaults for useful things.
#
DEBUG_BRIDGE_KM ?= 1
DEBUG_TRACE_BRIDGE_KM ?= 0
DEBUG_BRIDGE_KM_DISPATCH_TABLE ?= 0
+PVRSRV_LOG_MEMORY_ALLOCS ?= 0
+PVRSRV_DEBUG_OS_MEMORY ?= 0
+endif
+
+SUPPORT_DRI_DRM ?= $(SUPPORT_XORG)
+SUPPORT_DRI_DRM_EXT ?= 0
+
+SUPPORT_SECURE_FD_EXPORT = 1
+ifeq ($(SUPPORT_DRI_DRM),1)
+SUPPORT_SECURE_FD_EXPORT = 0
endif
+PVR_PROC_USE_SEQ_FILE ?= 1
TRANSFER_QUEUE ?= 1
SUPPORT_SGX_EVENT_OBJECT ?=1
SUPPORT_SECURE_HANDLES = 1
-SUPPORT_SECURE_FD_EXPORT = 1
SUPPORT_SRVINIT = 1
SUPPORT_PERCONTEXT_PB = 1
SUPPORT_LINUX_X86_PAT ?=1
SUPPORT_LINUX_X86_WRITECOMBINE ?=1
SUPPORT_SGX_LOW_LATENCY_SCHEDULING ?=1
+SUPPORT_OMAP3430_SGXFCLK_96M ?= 0
+SUPPORT_OMAP3430_OMAPFB3 ?= 0
+
+SUPPORT_CPU_CACHED_BUFFERS ?= 0
+
+SUPPORT_CACHEFLUSH_ON_ALLOC ?= 0
+SUPPORT_MEMINFO_IDS ?= 0
+
DC_NOHW_WIDTH ?= 640
DC_NOHW_HEIGHT ?= 480
+DISPLAY_CONTROLLER ?=
+
SYS_CFLAGS += -DSERVICES4 -D_XOPEN_SOURCE=600 -DPVR2D_VALIDATE_INPUT_PARAMS
+
# Thread support
USE_PTHREADS ?= 1
USE_GCC__thread_KEYWORD ?= 0
SYS_CFLAGS.$(DEBUG_BRIDGE_KM) += -DDEBUG_BRIDGE_KM
SYS_CFLAGS.$(DEBUG_TRACE_BRIDGE_KM) += -DDEBUG_TRACE_BRIDGE_KM
SYS_CFLAGS.$(DEBUG_BRIDGE_KM_DISPATCH_TABLE) += -DDEBUG_BRIDGE_KM_DISPATCH_TABLE
+SYS_CFLAGS.$(PVRSRV_LOG_MEMORY_ALLOCS) += -DPVRSRV_LOG_MEMORY_ALLOCS
+SYS_CFLAGS.$(PVRSRV_DEBUG_OS_MEMORY) += -DPVRSRV_DEBUG_OS_MEMORY
+SYS_CFLAGS.$(DEBUG_MESA_OGL_TRACE) += -DDEBUG_MESA_OGL_TRACE
SYS_CFLAGS.$(SUPPORT_LINUX_X86_WRITECOMBINE) += -DSUPPORT_LINUX_X86_WRITECOMBINE
SYS_CFLAGS.$(TRANSFER_QUEUE) += -DTRANSFER_QUEUE
SYS_CFLAGS.$(SUPPORT_SGX_MMU_DUMMY_PAGE) += -DSUPPORT_SGX_MMU_DUMMY_PAGE
+SYS_CFLAGS.$(PVRSRV_DUMP_MK_TRACE) += -DPVRSRV_DUMP_MK_TRACE
SYS_CFLAGS.$(PVRSRV_USSE_EDM_STATUS_DEBUG) += -DPVRSRV_USSE_EDM_STATUS_DEBUG
-SYS_CFLAGS.$(SGX_FEATURE_MP) += -DSGX_FEATURE_MP
-SYS_CFLAGS.$(SGX_FAST_DPM_INIT) += -DSGX_FAST_DPM_INIT
+SYS_CFLAGS.$(USE_SUPPORT_STATUSVALS_DEBUG) += -DUSE_SUPPORT_STATUSVALS_DEBUG
+SYS_CFLAGS.$(SGX_FAST_DPM_INIT) += -DSGX_FAST_DPM_INIT
+SYS_CFLAGS.$(SGX_DISABLE_UKERNEL_SECONDARY_STATE) += -DSGX_DISABLE_UKERNEL_SECONDARY_STATE
+SYS_CFLAGS.$(DBGBREAK_ON_SPM) += -DDBGBREAK_ON_SPM
+SYS_CFLAGS.$(PVR_DBG_BREAK_ASSERT_FAIL) += -DPVR_DBG_BREAK_ASSERT_FAIL
SYS_CFLAGS.$(NO_HARDWARE) += -DNO_HARDWARE
SYS_CFLAGS.$(SUPPORT_DRI_DRM) += -DSUPPORT_DRI_DRM
+SYS_CFLAGS.$(SUPPORT_DRI_DRM_EXT) += -DSUPPORT_DRI_DRM_EXT
SYS_CFLAGS.$(USE_PRIMARY_SURFACE_IN_FLIP_CHAIN) += -DUSE_PRIMARY_SURFACE_IN_FLIP_CHAIN
ifneq ("$(NO_HARDWARE)", "1")
SYS_CFLAGS.$(SUPPORT_LINUX_X86_PAT) += -DSUPPORT_LINUX_X86_PAT
+SYS_CFLAGS.$(SUPPORT_OMAP3430_SGXFCLK_96M) += -DSUPPORT_OMAP3430_SGXFCLK_96M
+SYS_CFLAGS.$(SUPPORT_OMAP3430_OMAPFB3) += -DSUPPORT_OMAP3430_OMAPFB3
+
+SYS_CFLAGS.$(SUPPORT_CPU_CACHED_BUFFERS) += -DSUPPORT_CPU_CACHED_BUFFERS
+SYS_CFLAGS.$(SUPPORT_CACHE_LINE_FLUSH) += -DSUPPORT_CACHE_LINE_FLUSH
+
+
+SYS_CFLAGS.$(SUPPORT_CACHEFLUSH_ON_ALLOC) += -DSUPPORT_CACHEFLUSH_ON_ALLOC
+SYS_CFLAGS.$(SUPPORT_MEMINFO_IDS) += -DSUPPORT_MEMINFO_IDS
+
+SYS_CFLAGS.$(SUPPORT_SGX_EDM_MEMORY_DEBUG) += -DSUPPORT_SGX_EDM_MEMORY_DEBUG
+
+SYS_CFLAGS.$(SUPPORT_ANDROID_PLATFORM) += -DSUPPORT_ANDROID_PLATFORM
+SYS_CFLAGS.$(SUPPORT_GRAPHICS_HAL) += -DSUPPORT_GRAPHICS_HAL
+SYS_CFLAGS.$(SUPPORT_GRAPHICS_HAL) += -DGRALLOC_VARIANT="\"$(GRALLOC_VARIANT)\""
+
+ifneq ("$(DISPLAY_CONTROLLER)", "")
+SYS_CFLAGS += -DDISPLAY_CONTROLLER=$(DISPLAY_CONTROLLER)
+endif
+
ifeq ("$(PVR_SYSTEM)", "sgx_nohw")
ifndef RTSIM
SYS_CFLAGS += -DNO_HARDWARE
endif
-SYS_CFLAGS += -DDC_NOHW_BUFFER_WIDTH=$(DC_NOHW_WIDTH) -DDC_NOHW_BUFFER_HEIGHT=$(DC_NOHW_HEIGHT)
+SYS_CFLAGS += -DDC_NOHW_BUFFER_WIDTH=$(DC_NOHW_WIDTH) -DDC_NOHW_BUFFER_HEIGHT=$(DC_NOHW_HEIGHT)
endif
ifeq ("$(PVR_SYSTEM)", "vgx_nohw")
SYS_CFLAGS += -DNO_HARDWARE -DDC_NOHW_BUFFER_WIDTH=$(DC_NOHW_WIDTH) -DDC_NOHW_BUFFER_HEIGHT=$(DC_NOHW_HEIGHT)
endif
-ifdef SGX_FEATURE_MP_CORE_COUNT
-SYS_CFLAGS += -DSGX_FEATURE_MP_CORE_COUNT=$(SGX_FEATURE_MP_CORE_COUNT)
-endif
+SYS_CFLAGS += -DDEBUG_LOG_PATH_TRUNCATE=\"$(EURASIAROOT)\"
+SYS_CFLAGS.$(PVR_PROC_USE_SEQ_FILE) += -DPVR_PROC_USE_SEQ_FILE
SYS_INCLUDES = -I$(EURASIAROOT)/include4 \
-I$(EURASIAROOT)/eurasiacon/includeext \
$(MODULE_CFLAGS) $(MODULE_CFLAGS.$(BUILD)) \
$(CORE) \
-Wall -fno-strict-aliasing \
- $(CFLAGS)
+ $(CFLAGS.$(BUILD))
#define _PVRVERSION_H_
#define PVRVERSION_MAJ 1
-#define PVRVERSION_MIN 4
-#define PVRVERSION_BRANCH 14
-#define PVRVERSION_BUILD 2616
-#define PVRVERSION_STRING "1.4.14.2616"
+#define PVRVERSION_MIN 5
+#define PVRVERSION_BRANCH 15
+#define PVRVERSION_BUILD 2766
+#define PVRVERSION_STRING "1.5.15.2766"
#define PVRVERSION_FILE "eurasiacon.pj"
#endif
IMG_UINT32 aui32DDKVersion[4];
-#if 0
+
IMG_BOOL bCPUCacheFlushAll;
IMG_BOOL bDeferCPUCacheFlush;
IMG_PVOID pvRangeAddrStart;
IMG_PVOID pvRangeAddrEnd;
-#endif
+
} PVRSRV_MISC_INFO;
} PVRSRV_DEVICE_CLASS;
+
typedef enum _PVRSRV_SYS_POWER_STATE_
{
PVRSRV_SYS_POWER_STATE_Unspecified = -1,
PVRSRV_DEV_POWER_STATE eNewPowerState,
PVRSRV_DEV_POWER_STATE eCurrentPowerState);
-
typedef PVRSRV_ERROR (*PFN_PRE_CLOCKSPEED_CHANGE) (IMG_HANDLE hDevHandle,
IMG_BOOL bIdleDevice,
PVRSRV_DEV_POWER_STATE eCurrentPowerState);
PVRSRV_DEV_POWER_STATE eCurrentPowerState);
-
typedef enum _PVRSRV_PIXEL_FORMAT_ {
PVRSRV_PIXEL_FORMAT_UNKNOWN = 0,
PVRSRV_PIXEL_FORMAT_IMC2 = 25,
PVRSRV_PIXEL_FORMAT_XRGB8888,
PVRSRV_PIXEL_FORMAT_XBGR8888,
+ PVRSRV_PIXEL_FORMAT_BGRA8888,
PVRSRV_PIXEL_FORMAT_XRGB4444,
PVRSRV_PIXEL_FORMAT_ARGB8332,
PVRSRV_PIXEL_FORMAT_A2RGB10,
PVRSRV_PIXEL_FORMAT_BGR32,
PVRSRV_PIXEL_FORMAT_GR32,
PVRSRV_PIXEL_FORMAT_E5BGR9,
-
+
PVRSRV_PIXEL_FORMAT_DXT1,
- PVRSRV_PIXEL_FORMAT_DXT23,
- PVRSRV_PIXEL_FORMAT_DXT45,
-
+ PVRSRV_PIXEL_FORMAT_DXT2,
+ PVRSRV_PIXEL_FORMAT_DXT3,
+ PVRSRV_PIXEL_FORMAT_DXT4,
+ PVRSRV_PIXEL_FORMAT_DXT5,
+
PVRSRV_PIXEL_FORMAT_R8G8_B8G8,
PVRSRV_PIXEL_FORMAT_G8R8_G8B8,
-
+
PVRSRV_PIXEL_FORMAT_NV11,
PVRSRV_PIXEL_FORMAT_NV12,
-
+
PVRSRV_PIXEL_FORMAT_YUY2,
PVRSRV_PIXEL_FORMAT_YUV420,
PVRSRV_PIXEL_FORMAT_YVYU,
PVRSRV_PIXEL_FORMAT_UYVY,
PVRSRV_PIXEL_FORMAT_VYUY,
-
+
PVRSRV_PIXEL_FORMAT_FOURCC_ORG_UYVY,
PVRSRV_PIXEL_FORMAT_FOURCC_ORG_YUYV,
PVRSRV_PIXEL_FORMAT_FOURCC_ORG_YVYU,
PVRSRV_PIXEL_FORMAT_FOURCC_ORG_VYUY,
-
+ PVRSRV_PIXEL_FORMAT_FOURCC_ORG_AYUV,
+
PVRSRV_PIXEL_FORMAT_A32B32G32R32,
PVRSRV_PIXEL_FORMAT_A32B32G32R32F,
PVRSRV_PIXEL_FORMAT_A32B32G32R32_UINT,
PVRSRV_PIXEL_FORMAT_A32B32G32R32_SINT,
-
+
PVRSRV_PIXEL_FORMAT_B32G32R32,
PVRSRV_PIXEL_FORMAT_B32G32R32F,
PVRSRV_PIXEL_FORMAT_B32G32R32_UINT,
PVRSRV_PIXEL_FORMAT_B32G32R32_SINT,
-
+
PVRSRV_PIXEL_FORMAT_G32R32,
PVRSRV_PIXEL_FORMAT_G32R32F,
PVRSRV_PIXEL_FORMAT_G32R32_UINT,
PVRSRV_PIXEL_FORMAT_G32R32_SINT,
-
+
PVRSRV_PIXEL_FORMAT_D32F,
PVRSRV_PIXEL_FORMAT_R32,
PVRSRV_PIXEL_FORMAT_R32F,
PVRSRV_PIXEL_FORMAT_R32_UINT,
PVRSRV_PIXEL_FORMAT_R32_SINT,
-
+
PVRSRV_PIXEL_FORMAT_A16B16G16R16,
PVRSRV_PIXEL_FORMAT_A16B16G16R16F,
PVRSRV_PIXEL_FORMAT_R16_UNORM,
PVRSRV_PIXEL_FORMAT_R16_SINT,
PVRSRV_PIXEL_FORMAT_R16_SNORM,
-
+
+
+ PVRSRV_PIXEL_FORMAT_X8R8G8B8,
+ PVRSRV_PIXEL_FORMAT_X8R8G8B8_UNORM,
+ PVRSRV_PIXEL_FORMAT_X8R8G8B8_UNORM_SRGB,
+
+ PVRSRV_PIXEL_FORMAT_A8R8G8B8,
+ PVRSRV_PIXEL_FORMAT_A8R8G8B8_UNORM,
+ PVRSRV_PIXEL_FORMAT_A8R8G8B8_UNORM_SRGB,
PVRSRV_PIXEL_FORMAT_A8B8G8R8,
PVRSRV_PIXEL_FORMAT_A8B8G8R8_UINT,
PVRSRV_PIXEL_FORMAT_A8B8G8R8_UNORM,
+ PVRSRV_PIXEL_FORMAT_A8B8G8R8_UNORM_SRGB,
PVRSRV_PIXEL_FORMAT_A8B8G8R8_SINT,
PVRSRV_PIXEL_FORMAT_A8B8G8R8_SNORM,
-
+
PVRSRV_PIXEL_FORMAT_G8R8,
PVRSRV_PIXEL_FORMAT_G8R8_UINT,
PVRSRV_PIXEL_FORMAT_G8R8_UNORM,
PVRSRV_PIXEL_FORMAT_G8R8_SINT,
PVRSRV_PIXEL_FORMAT_G8R8_SNORM,
-
+
PVRSRV_PIXEL_FORMAT_A8,
PVRSRV_PIXEL_FORMAT_R8,
PVRSRV_PIXEL_FORMAT_R8_UNORM,
PVRSRV_PIXEL_FORMAT_R8_SINT,
PVRSRV_PIXEL_FORMAT_R8_SNORM,
-
+
PVRSRV_PIXEL_FORMAT_A2B10G10R10,
PVRSRV_PIXEL_FORMAT_A2B10G10R10_UNORM,
PVRSRV_PIXEL_FORMAT_A2B10G10R10_UINT,
-
+
PVRSRV_PIXEL_FORMAT_B10G11R11,
PVRSRV_PIXEL_FORMAT_B10G11R11F,
-
+
PVRSRV_PIXEL_FORMAT_X24G8R32,
PVRSRV_PIXEL_FORMAT_G8R24,
- PVRSRV_PIXEL_FORMAT_E5B9G9R9,
+ PVRSRV_PIXEL_FORMAT_X8R24,
+ PVRSRV_PIXEL_FORMAT_E5B9G9R9,
PVRSRV_PIXEL_FORMAT_R1,
-
+
PVRSRV_PIXEL_FORMAT_BC1,
PVRSRV_PIXEL_FORMAT_BC1_UNORM,
PVRSRV_PIXEL_FORMAT_BC1_SRGB,
PVRSRV_PIXEL_FORMAT_BC5,
PVRSRV_PIXEL_FORMAT_BC5_UNORM,
PVRSRV_PIXEL_FORMAT_BC5_SNORM,
-
+
+
+ PVRSRV_PIXEL_FORMAT_L_F16,
+ PVRSRV_PIXEL_FORMAT_L_F16_REP,
+ PVRSRV_PIXEL_FORMAT_L_F16_A_F16,
+ PVRSRV_PIXEL_FORMAT_A_F16,
+ PVRSRV_PIXEL_FORMAT_B16G16R16F,
+
+ PVRSRV_PIXEL_FORMAT_L_F32,
+ PVRSRV_PIXEL_FORMAT_A_F32,
+ PVRSRV_PIXEL_FORMAT_L_F32_A_F32,
+
+
+ PVRSRV_PIXEL_FORMAT_PVRTC2,
+ PVRSRV_PIXEL_FORMAT_PVRTC4,
+ PVRSRV_PIXEL_FORMAT_PVRTCII2,
+ PVRSRV_PIXEL_FORMAT_PVRTCII4,
+ PVRSRV_PIXEL_FORMAT_PVRTCIII,
+ PVRSRV_PIXEL_FORMAT_PVRO8,
+ PVRSRV_PIXEL_FORMAT_PVRO88,
+ PVRSRV_PIXEL_FORMAT_PT1,
+ PVRSRV_PIXEL_FORMAT_PT2,
+ PVRSRV_PIXEL_FORMAT_PT4,
+ PVRSRV_PIXEL_FORMAT_PT8,
+ PVRSRV_PIXEL_FORMAT_PTW,
+ PVRSRV_PIXEL_FORMAT_PTB,
+ PVRSRV_PIXEL_FORMAT_MONO8,
+ PVRSRV_PIXEL_FORMAT_MONO16,
+
+
+ PVRSRV_PIXEL_FORMAT_C0_YUYV,
+ PVRSRV_PIXEL_FORMAT_C0_UYVY,
+ PVRSRV_PIXEL_FORMAT_C0_YVYU,
+ PVRSRV_PIXEL_FORMAT_C0_VYUY,
+ PVRSRV_PIXEL_FORMAT_C1_YUYV,
+ PVRSRV_PIXEL_FORMAT_C1_UYVY,
+ PVRSRV_PIXEL_FORMAT_C1_YVYU,
+ PVRSRV_PIXEL_FORMAT_C1_VYUY,
+
+
+ PVRSRV_PIXEL_FORMAT_C0_YUV420_2P_UV,
+ PVRSRV_PIXEL_FORMAT_C0_YUV420_2P_VU,
+ PVRSRV_PIXEL_FORMAT_C0_YUV420_3P,
+ PVRSRV_PIXEL_FORMAT_C1_YUV420_2P_UV,
+ PVRSRV_PIXEL_FORMAT_C1_YUV420_2P_VU,
+ PVRSRV_PIXEL_FORMAT_C1_YUV420_3P,
+
+ PVRSRV_PIXEL_FORMAT_A2B10G10R10F,
+ PVRSRV_PIXEL_FORMAT_B8G8R8_SINT,
+ PVRSRV_PIXEL_FORMAT_PVRF32SIGNMASK,
+
PVRSRV_PIXEL_FORMAT_FORCE_I32 = 0x7fffffff,
} PVRSRV_PIXEL_FORMAT;
#define OPTIONS_BIT12 0x0
#endif
-#if defined(SGX_FEATURE_RENDER_TARGET_ARRAYS) || defined (INTERNAL_TEST)
-#define SGX_FEATURE_RENDER_TARGET_ARRAYS_SET_OFFSET OPTIONS_BIT13
+
+#if defined(SGX_FEATURE_SYSTEM_CACHE) || defined (INTERNAL_TEST)
+#define SGX_FEATURE_SYSTEM_CACHE_SET_OFFSET OPTIONS_BIT13
#define OPTIONS_BIT13 (0x1 << 13)
#else
#define OPTIONS_BIT13 0x0
#endif
-#if defined(SGX_FEATURE_SYSTEM_CACHE) || defined (INTERNAL_TEST)
-#define SGX_FEATURE_SYSTEM_CACHE_SET_OFFSET OPTIONS_BIT14
+#if defined(SGX_SUPPORT_HWPROFILING) || defined (INTERNAL_TEST)
+#define SGX_SUPPORT_HWPROFILING_SET_OFFSET OPTIONS_BIT14
#define OPTIONS_BIT14 (0x1 << 14)
#else
#define OPTIONS_BIT14 0x0
#endif
-#if defined(SGX_SUPPORT_HWPROFILING) || defined (INTERNAL_TEST)
-#define SGX_SUPPORT_HWPROFILING_SET_OFFSET OPTIONS_BIT15
+
+
+#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT) || defined (INTERNAL_TEST)
+#define SUPPORT_ACTIVE_POWER_MANAGEMENT_SET_OFFSET OPTIONS_BIT15
#define OPTIONS_BIT15 (0x1 << 15)
#else
#define OPTIONS_BIT15 0x0
#endif
-
-
-#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT) || defined (INTERNAL_TEST)
-#define SUPPORT_ACTIVE_POWER_MANAGEMENT_SET_OFFSET OPTIONS_BIT16
+#if defined(SUPPORT_DISPLAYCONTROLLER_TILING) || defined (INTERNAL_TEST)
+#define SUPPORT_DISPLAYCONTROLLER_TILING_SET_OFFSET OPTIONS_BIT16
#define OPTIONS_BIT16 (0x1 << 16)
#else
#define OPTIONS_BIT16 0x0
#endif
-#if defined(SUPPORT_DISPLAYCONTROLLER_TILING) || defined (INTERNAL_TEST)
-#define SUPPORT_DISPLAYCONTROLLER_TILING_SET_OFFSET OPTIONS_BIT17
+#if defined(SUPPORT_PERCONTEXT_PB) || defined (INTERNAL_TEST)
+#define SUPPORT_PERCONTEXT_PB_SET_OFFSET OPTIONS_BIT17
#define OPTIONS_BIT17 (0x1 << 17)
#else
#define OPTIONS_BIT17 0x0
#endif
-#if defined(SUPPORT_PERCONTEXT_PB) || defined (INTERNAL_TEST)
-#define SUPPORT_PERCONTEXT_PB_SET_OFFSET OPTIONS_BIT18
+#if defined(SUPPORT_SGX_HWPERF) || defined (INTERNAL_TEST)
+#define SUPPORT_SGX_HWPERF_SET_OFFSET OPTIONS_BIT18
#define OPTIONS_BIT18 (0x1 << 18)
#else
#define OPTIONS_BIT18 0x0
#endif
-#if defined(SUPPORT_SGX_HWPERF) || defined (INTERNAL_TEST)
-#define SUPPORT_SGX_HWPERF_SET_OFFSET OPTIONS_BIT19
+
+
+#if defined(SUPPORT_SGX_MMU_DUMMY_PAGE) || defined (INTERNAL_TEST)
+#define SUPPORT_SGX_MMU_DUMMY_PAGE_SET_OFFSET OPTIONS_BIT19
#define OPTIONS_BIT19 (0x1 << 19)
#else
#define OPTIONS_BIT19 0x0
#endif
-
-
-#if defined(SUPPORT_SGX_MMU_DUMMY_PAGE) || defined (INTERNAL_TEST)
-#define SUPPORT_SGX_MMU_DUMMY_PAGE_SET_OFFSET OPTIONS_BIT20
+#if defined(SUPPORT_SGX_PRIORITY_SCHEDULING) || defined (INTERNAL_TEST)
+#define SUPPORT_SGX_PRIORITY_SCHEDULING_SET_OFFSET OPTIONS_BIT20
#define OPTIONS_BIT20 (0x1 << 20)
#else
#define OPTIONS_BIT20 0x0
#endif
-#if defined(SUPPORT_SGX_PRIORITY_SCHEDULING) || defined (INTERNAL_TEST)
-#define SUPPORT_SGX_PRIORITY_SCHEDULING_SET_OFFSET OPTIONS_BIT21
+#if defined(SGX_LOW_LATENCY_SCHEDULING) || defined (INTERNAL_TEST)
+#define SUPPORT_SGX_LOW_LATENCY_SCHEDULING_SET_OFFSET OPTIONS_BIT21
#define OPTIONS_BIT21 (0x1 << 21)
#else
#define OPTIONS_BIT21 0x0
OPTIONS_BIT19 |\
OPTIONS_BIT20 |\
OPTIONS_BIT21 |\
- OPTIONS_BIT22 |\
OPTIONS_HIGHBYTE
#define SGX_MAX_TA_STATUS_VALS 32
-#if 0
#define SGX_MAX_3D_STATUS_VALS 3
-#else
-#define SGX_MAX_3D_STATUS_VALS 2
-#endif
#if defined(SUPPORT_SGX_GENERALISED_SYNCOBJECTS)
#define SGX_MAX_TA_DST_SYNCS 1
#define PVRSRV_BRIDGE_EVENT_OBJECT_CMD_LAST (PVRSRV_BRIDGE_EVENT_OBJECT_CMD_FIRST+2)
#define PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST (PVRSRV_BRIDGE_EVENT_OBJECT_CMD_LAST+1)
-#define PVRSRV_BRIDGE_MODIFY_SYNC_OPS PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+0)
-#define PVRSRV_BRIDGE_SYNC_OPS_CMD_LAST (PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+0)
+#define PVRSRV_BRIDGE_MODIFY_PENDING_SYNC_OPS PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+0)
+#define PVRSRV_BRIDGE_MODIFY_COMPLETE_SYNC_OPS PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+1)
+#define PVRSRV_BRIDGE_SYNC_OPS_CMD_LAST (PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+1)
#define PVRSRV_BRIDGE_LAST_NON_DEVICE_CMD (PVRSRV_BRIDGE_SYNC_OPS_CMD_LAST+1)
IMG_UINT32 ui32Offset;
IMG_UINT32 ui32Value;
IMG_UINT32 ui32Mask;
- IMG_BOOL bLastFrame;
- IMG_BOOL bOverwrite;
+ IMG_UINT32 ui32Flags;
}PVRSRV_BRIDGE_IN_PDUMP_MEMPOL;
{
PVRSRV_ERROR eError;
IMG_HANDLE hMemInfo;
+#if defined(SUPPORT_MEMINFO_IDS)
+ IMG_UINT64 ui64Stamp;
+#endif
} PVRSRV_BRIDGE_OUT_EXPORTDEVICEMEM;
IMG_HANDLE hOSEventKM;
} PVRSRV_BRIDGE_IN_EVENT_OBJECT_CLOSE;
-
-typedef struct PVRSRV_BRIDGE_IN_MODIFY_SYNC_OPS_TAG
+typedef struct PVRSRV_BRIDGE_IN_MODIFY_PENDING_SYNC_OPS_TAG
+{
+ IMG_UINT32 ui32BridgeFlags;
+ IMG_HANDLE hKernelSyncInfo;
+ IMG_UINT32 ui32ModifyFlags;
+
+} PVRSRV_BRIDGE_IN_MODIFY_PENDING_SYNC_OPS;
+
+typedef struct PVRSRV_BRIDGE_IN_MODIFY_COMPLETE_SYNC_OPS_TAG
{
IMG_UINT32 ui32BridgeFlags;
IMG_HANDLE hKernelSyncInfo;
IMG_UINT32 ui32ModifyFlags;
-} PVRSRV_BRIDGE_IN_MODIFY_SYNC_OPS;
+} PVRSRV_BRIDGE_IN_MODIFY_COMPLETE_SYNC_OPS;
-typedef struct PVRSRV_BRIDGE_OUT_MODIFY_SYNC_OPS_TAG
+typedef struct PVRSRV_BRIDGE_OUT_MODIFY_PENDING_SYNC_OPS_TAG
{
PVRSRV_ERROR eError;
IMG_UINT32 ui32ReadOpsPending;
- IMG_UINT32 ui32ReadOpsComplete;
IMG_UINT32 ui32WriteOpsPending;
- IMG_UINT32 ui32WriteOpsComplete;
-} PVRSRV_BRIDGE_OUT_MODIFY_SYNC_OPS;
+} PVRSRV_BRIDGE_OUT_MODIFY_PENDING_SYNC_OPS;
#if defined (__cplusplus)
}
#define PVRSRV_BRIDGE_SGX_DOKICK PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+3)
#define PVRSRV_BRIDGE_SGX_GETPHYSPAGEADDR PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+4)
#define PVRSRV_BRIDGE_SGX_READREGISTRYDWORD PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+5)
-#define PVRSRV_BRIDGE_SGX_SCHEDULECOMMAND PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+6)
#define PVRSRV_BRIDGE_SGX_2DQUERYBLTSCOMPLETE PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+9)
IMG_UINT32 ui32Data;
}PVRSRV_BRIDGE_OUT_READREGDWORD;
-
-typedef struct PVRSRV_BRIDGE_IN_SCHEDULECOMMAND_TAG
-{
- IMG_UINT32 ui32BridgeFlags;
- IMG_HANDLE hDevCookie;
- SGXMKIF_COMMAND_TYPE eCommandType;
- SGXMKIF_COMMAND *psCommandData;
-
-}PVRSRV_BRIDGE_IN_SCHEDULECOMMAND;
typedef struct PVRSRV_BRIDGE_IN_SGXGETMISCINFO_TAG
{
IMG_HANDLE hSharedPBDescKernelMemInfoHandle;
IMG_HANDLE hHWPBDescKernelMemInfoHandle;
IMG_HANDLE hBlockKernelMemInfoHandle;
+ IMG_HANDLE hHWBlockKernelMemInfoHandle;
IMG_HANDLE ahSharedPBDescSubKernelMemInfoHandles[PVRSRV_BRIDGE_SGX_SHAREDPBDESC_MAX_SUBMEMINFOS];
IMG_UINT32 ui32SharedPBDescSubKernelMemInfoHandlesCount;
PVRSRV_ERROR eError;
IMG_HANDLE hSharedPBDescKernelMemInfo;
IMG_HANDLE hHWPBDescKernelMemInfo;
IMG_HANDLE hBlockKernelMemInfo;
+ IMG_HANDLE hHWBlockKernelMemInfo;
IMG_UINT32 ui32TotalPBSize;
IMG_HANDLE *phKernelMemInfoHandles;
IMG_UINT32 ui32KernelMemInfoHandlesCount;
typedef struct PVRSRV_BRIDGE_IN_PDUMP_3D_SIGNATURE_REGISTERS_TAG
{
IMG_UINT32 ui32BridgeFlags;
+ IMG_HANDLE hDevCookie;
IMG_UINT32 ui32DumpFrameNum;
IMG_BOOL bLastFrame;
IMG_UINT32 *pui32Registers;
typedef struct PVRSRV_BRIDGE_IN_PDUMP_TA_SIGNATURE_REGISTERS_TAG
{
IMG_UINT32 ui32BridgeFlags;
+ IMG_HANDLE hDevCookie;
IMG_UINT32 ui32DumpFrameNum;
IMG_UINT32 ui32TAKickCount;
IMG_BOOL bLastFrame;
IMG_UINT32 ui32New;
IMG_UINT32 ui32NewReset;
IMG_UINT32 ui32CountersReg;
+ IMG_UINT32 ui32Reg2;
} PVRSRV_BRIDGE_IN_SGX_READ_DIFF_COUNTERS;
typedef struct PVRSRV_BRIDGE_OUT_SGX_READ_DIFF_COUNTERS_TAG
{
PVRSRV_ERROR eError;
IMG_UINT32 ui32Old;
- IMG_UINT32 ui32Time;
IMG_BOOL bActive;
PVRSRV_SGXDEV_DIFF_INFO sDiffs;
} PVRSRV_BRIDGE_OUT_SGX_READ_DIFF_COUNTERS;
typedef struct _SGXMKIF_COMMAND_
{
IMG_UINT32 ui32ServiceAddress;
- IMG_UINT32 ui32Data[2];
IMG_UINT32 ui32CacheControl;
+ IMG_UINT32 ui32Data[2];
} SGXMKIF_COMMAND;
typedef struct _SGXMKIF_HOST_CTL_
{
+#if defined(PVRSRV_USSE_EDM_BREAKPOINTS)
+ IMG_UINT32 ui32BreakpointDisable;
+ IMG_UINT32 ui32Continue;
+#endif
- volatile IMG_UINT32 ui32PowerStatus;
+ volatile IMG_UINT32 ui32InitStatus;
+ volatile IMG_UINT32 ui32PowerStatus;
+ volatile IMG_UINT32 ui32CleanupStatus;
#if defined(SUPPORT_HW_RECOVERY)
- IMG_UINT32 ui32uKernelDetectedLockups;
- IMG_UINT32 ui32HostDetectedLockups;
- IMG_UINT32 ui32HWRecoverySampleRate;
+ IMG_UINT32 ui32uKernelDetectedLockups;
+ IMG_UINT32 ui32HostDetectedLockups;
+ IMG_UINT32 ui32HWRecoverySampleRate;
#endif
- IMG_UINT32 ui32ActivePowManSampleRate;
- IMG_UINT32 ui32InterruptFlags;
- IMG_UINT32 ui32InterruptClearFlags;
+ IMG_UINT32 ui32uKernelTimerClock;
+ IMG_UINT32 ui32ActivePowManSampleRate;
+ IMG_UINT32 ui32InterruptFlags;
+ IMG_UINT32 ui32InterruptClearFlags;
- IMG_UINT32 ui32ResManFlags;
- IMG_DEV_VIRTADDR sResManCleanupData;
IMG_UINT32 ui32NumActivePowerEvents;
#define SGXMKIF_CMDTA_CTRLFLAGS_READY 0x00000001
typedef struct _SGXMKIF_CMDTA_SHARED_
{
+ IMG_UINT32 ui32CtrlFlags;
+
IMG_UINT32 ui32NumTAStatusVals;
IMG_UINT32 ui32Num3DStatusVals;
#endif
+ PVRSRV_DEVICE_SYNC_OBJECT sTA3DDependency;
+
CTL_STATUS sCtlTAStatusInfo[SGX_MAX_TA_STATUS_VALS];
CTL_STATUS sCtl3DStatusInfo[SGX_MAX_3D_STATUS_VALS];
- PVRSRV_DEVICE_SYNC_OBJECT sTA3DDependency;
-
} SGXMKIF_CMDTA_SHARED;
#define SGXTQ_MAX_STATUS SGX_MAX_TRANSFER_STATUS_VALS + 2
#endif
-typedef enum _SGXMKIF_COMMAND_TYPE_
-{
- SGXMKIF_COMMAND_EDM_KICK = 0,
- SGXMKIF_COMMAND_VIDEO_KICK = 1,
- SGXMKIF_COMMAND_REQUEST_SGXMISCINFO = 2,
-
- SGXMKIF_COMMAND_FORCE_I32 = -1,
-
-}SGXMKIF_COMMAND_TYPE;
-
-#define PVRSRV_CCBFLAGS_RASTERCMD 0x1
-#define PVRSRV_CCBFLAGS_TRANSFERCMD 0x2
-#define PVRSRV_CCBFLAGS_PROCESS_QUEUESCMD 0x3
-#if defined(SGX_FEATURE_2D_HARDWARE)
-#define PVRSRV_CCBFLAGS_2DCMD 0x4
-#endif
-#define PVRSRV_CCBFLAGS_POWERCMD 0x5
-
#define PVRSRV_CLEANUPCMD_RT 0x1
#define PVRSRV_CLEANUPCMD_RC 0x2
#define PVRSRV_CLEANUPCMD_TC 0x3
{
IMG_UINT32 ui32MiscInfoFlags;
PVRSRV_SGX_MISCINFO_FEATURES sSGXFeatures;
+ SGX_MISCINFO_STRUCT_SIZES sSGXStructSizes;
#if defined(SUPPORT_SGX_EDM_MEMORY_DEBUG)
PVRSRV_SGX_MISCINFO_MEMREAD sSGXMemReadData;
#endif
typedef enum _SGXMKIF_CMD_TYPE_
{
-#if 0
SGXMKIF_CMD_TA = 0,
SGXMKIF_CMD_TRANSFER = 1,
SGXMKIF_CMD_2D = 2,
SGXMKIF_CMD_GETMISCINFO = 5,
SGXMKIF_CMD_PROCESS_QUEUES = 6,
SGXMKIF_CMD_MAX = 7,
-#else
- SGXMKIF_CMD_GETMISCINFO = 0,
- SGXMKIF_CMD_TA = 1,
- SGXMKIF_CMD_TRANSFER = 2,
- SGXMKIF_CMD_PROCESS_QUEUES = 3,
- SGXMKIF_CMD_2D = 4,
- SGXMKIF_CMD_POWER = 5,
-// SGXMKIF_CMD_CLEANUP = 0,
- SGXMKIF_CMD_MAX = 6,
-#endif
+
SGXMKIF_CMD_FORCE_I32 = -1,
} SGXMKIF_CMD_TYPE;
IMG_HANDLE hKernelSGXHostCtlMemInfo;
IMG_HANDLE hKernelSGXTA3DCtlMemInfo;
IMG_HANDLE hKernelSGXMiscMemInfo;
- IMG_UINT32 ui32HostKickAddress;
- IMG_UINT32 ui32GetMiscInfoAddress;
+
+ IMG_UINT32 aui32HostKickAddr[SGXMKIF_CMD_MAX];
+
+ SGX_INIT_SCRIPTS sScripts;
+
+ IMG_UINT32 ui32ClientBuildOptions;
+ SGX_MISCINFO_STRUCT_SIZES sSGXStructSizes;
+
#if defined(SGX_SUPPORT_HWPROFILING)
IMG_HANDLE hKernelHWProfilingMemInfo;
#endif
IMG_UINT32 asInitDevData[SGX_MAX_DEV_DATA];
IMG_HANDLE asInitMemHandles[SGX_MAX_INIT_MEM_HANDLES];
- SGX_INIT_SCRIPTS sScripts;
-
} SGX_BRIDGE_INIT_INFO;
typedef struct _SGX_CCB_KICK_
{
- SGXMKIF_COMMAND_TYPE eCommand;
SGXMKIF_COMMAND sCommand;
IMG_HANDLE hCCBKernelMemInfo;
IMG_UINT32 ui32NumDstSyncObjects;
IMG_HANDLE hKernelHWSyncListMemInfo;
-#if defined(SGX_FEATURE_RENDER_TARGET_ARRAYS)
- IMG_HANDLE *pasDstSyncHandles;
-#else
- IMG_HANDLE sDstSyncHandle;
-#endif
+
+
+ IMG_HANDLE *pahDstSyncHandles;
IMG_UINT32 ui32NumTAStatusVals;
IMG_UINT32 ui32Num3DStatusVals;
typedef struct _PVRSRV_SGXDEV_DIFF_INFO_
{
IMG_UINT32 aui32Counters[PVRSRV_SGX_DIFF_NUM_COUNTERS];
- IMG_UINT32 ui32Time[2];
+ IMG_UINT32 ui32Time[3];
IMG_UINT32 ui32Marker[2];
} PVRSRV_SGXDEV_DIFF_INFO, *PPVRSRV_SGXDEV_DIFF_INFO;
return 0;
}
-#if 0
+
typedef struct _MODIFY_SYNC_OP_INFO
{
PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
return 0;
}
-#endif
+
PVRSRV_ERROR
CommonBridgeInit(IMG_VOID)
SetDispatchTableEntry(PVRSRV_BRIDGE_EVENT_OBJECT_WAIT, PVRSRVEventObjectWaitBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_EVENT_OBJECT_OPEN, PVRSRVEventObjectOpenBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_EVENT_OBJECT_CLOSE, PVRSRVEventObjectCloseBW);
-#if 0
+
SetDispatchTableEntry(PVRSRV_BRIDGE_MODIFY_PENDING_SYNC_OPS, PVRSRVModifyPendingSyncOpsBW);
SetDispatchTableEntry(PVRSRV_BRIDGE_MODIFY_COMPLETE_SYNC_OPS, PVRSRVModifyCompleteSyncOpsBW);
-#endif
+
#if defined (SUPPORT_SGX)
SetSGXDispatchTableEntry();
#endif
#endif
}PVRSRV_BRIDGE_DISPATCH_TABLE_ENTRY;
-#if defined(SUPPORT_VGX)
-#define BRIDGE_DISPATCH_TABLE_ENTRY_COUNT (PVRSRV_BRIDGE_LAST_VGX_CMD+1)
-#define PVRSRV_BRIDGE_LAST_DEVICE_CMD PVRSRV_BRIDGE_LAST_VGX_CMD
+#if defined(SUPPORT_VGX) || defined(SUPPORT_MSVDX)
+ #if defined(SUPPORT_VGX)
+ #define BRIDGE_DISPATCH_TABLE_ENTRY_COUNT (PVRSRV_BRIDGE_LAST_VGX_CMD+1)
+ #define PVRSRV_BRIDGE_LAST_DEVICE_CMD PVRSRV_BRIDGE_LAST_VGX_CMD
+ #else
+ #define BRIDGE_DISPATCH_TABLE_ENTRY_COUNT (PVRSRV_BRIDGE_LAST_MSVDX_CMD+1)
+ #define PVRSRV_BRIDGE_LAST_DEVICE_CMD PVRSRV_BRIDGE_LAST_MSVDX_CMD
+ #endif
#else
-
-#if defined(SUPPORT_SGX)
-#define BRIDGE_DISPATCH_TABLE_ENTRY_COUNT (PVRSRV_BRIDGE_LAST_SGX_CMD+1)
-#define PVRSRV_BRIDGE_LAST_DEVICE_CMD PVRSRV_BRIDGE_LAST_SGX_CMD
-#else
-#define BRIDGE_DISPATCH_TABLE_ENTRY_COUNT (PVRSRV_BRIDGE_LAST_NON_DEVICE_CMD+1)
-#define PVRSRV_BRIDGE_LAST_DEVICE_CMD PVRSRV_BRIDGE_LAST_NON_DEVICE_CMD
-#endif
-
+ #if defined(SUPPORT_SGX)
+ #define BRIDGE_DISPATCH_TABLE_ENTRY_COUNT (PVRSRV_BRIDGE_LAST_SGX_CMD+1)
+ #define PVRSRV_BRIDGE_LAST_DEVICE_CMD PVRSRV_BRIDGE_LAST_SGX_CMD
+ #else
+ #define BRIDGE_DISPATCH_TABLE_ENTRY_COUNT (PVRSRV_BRIDGE_LAST_NON_DEVICE_CMD+1)
+ #define PVRSRV_BRIDGE_LAST_DEVICE_CMD PVRSRV_BRIDGE_LAST_NON_DEVICE_CMD
+ #endif
#endif
extern PVRSRV_BRIDGE_DISPATCH_TABLE_ENTRY g_BridgeDispatchTable[BRIDGE_DISPATCH_TABLE_ENTRY_COUNT];
if(ui32NumDstSyncs > 0)
{
-#if 0
if(!OSAccessOK(PVR_VERIFY_READ,
psDoKickIN->sCCBKick.pahDstSyncHandles,
ui32NumDstSyncs * sizeof(IMG_HANDLE)))
}
}
-#else
- psRetOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
- &psDoKickIN->sCCBKick.sDstSyncHandle,
- psDoKickIN->sCCBKick.sDstSyncHandle,
- PVRSRV_HANDLE_TYPE_SYNC_INFO);
- if(psRetOUT->eError != PVRSRV_OK)
- {
- goto PVRSRV_BRIDGE_SGX_DOKICK_RETURN_RESULT;
- }
-#endif
psRetOUT->eError =
PVRSRVLookupHandle(psPerProc->psHandleBase,
&psDoKickIN->sCCBKick.hKernelHWSyncListMemInfo,
psSGXReadDiffCountersIN->ui32New,
psSGXReadDiffCountersIN->ui32NewReset,
psSGXReadDiffCountersIN->ui32CountersReg,
-#if 0
psSGXReadDiffCountersIN->ui32Reg2,
-#else
- 0,
-#endif
&psSGXReadDiffCountersOUT->bActive,
&psSGXReadDiffCountersOUT->sDiffs);
PVRSRV_HANDLE_TYPE_MEM_INFO_REF,
PVRSRV_HANDLE_ALLOC_FLAG_MULTI,
psSGXFindSharedPBDescOUT->hSharedPBDesc);
-#if 0
+
PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
&psSGXFindSharedPBDescOUT->hHWBlockKernelMemInfoHandle,
psHWBlockKernelMemInfo,
PVRSRV_HANDLE_TYPE_MEM_INFO_REF,
PVRSRV_HANDLE_ALLOC_FLAG_MULTI,
psSGXFindSharedPBDescOUT->hSharedPBDesc);
-#endif
+
for(i=0; i<ui32SharedPBDescSubKernelMemInfosCount; i++)
{
{
goto PVRSRV_BRIDGE_SGX_ADDSHAREDPBDESC_RETURN_RESULT;
}
-#if 0
+
eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
(IMG_VOID **)&psHWBlockKernelMemInfo,
psSGXAddSharedPBDescIN->hHWBlockKernelMemInfo,
{
goto PVRSRV_BRIDGE_SGX_ADDSHAREDPBDESC_RETURN_RESULT;
}
-#else
- psHWBlockKernelMemInfo = NULL;
-#endif
+
if(!OSAccessOK(PVR_VERIFY_READ,
psSGXAddSharedPBDescIN->phKernelMemInfoHandles,
PVRSRV_HANDLE_TYPE_SHARED_SYS_MEM_INFO);
PVR_ASSERT(eError == PVRSRV_OK);
-#if 0
+
eError = PVRSRVReleaseHandle(psPerProc->psHandleBase,
psSGXAddSharedPBDescIN->hHWBlockKernelMemInfo,
PVRSRV_HANDLE_TYPE_MEM_INFO);
PVR_ASSERT(eError == PVRSRV_OK);
-#endif
+
for(i=0; i<ui32KernelMemInfoHandlesCount; i++)
{
{
goto NoAdd;
}
-#if 0
+
if(PVRSRVDissociateMemFromResmanKM(psHWBlockKernelMemInfo)
!= PVRSRV_OK)
{
goto NoAdd;
}
-#endif
+
psStubPBDesc->ui32RefCount = 1;
psStubPBDesc->ui32TotalPBSize = ui32TotalPBSize;
psStubPBDesc->psSharedPBDescKernelMemInfo = psSharedPBDescKernelMemInfo;
#ifndef __SGXCONFIG_H__
#define __SGXCONFIG_H__
+#include "sgxdefs.h"
+
#define DEV_DEVICE_TYPE PVRSRV_DEVICE_TYPE_SGX
#define DEV_DEVICE_CLASS PVRSRV_DEVICE_CLASS_3D
#if defined(SGX_FEATURE_2D_HARDWARE)
#define SGX_2D_HEAP_BASE 0x00100000
#define SGX_2D_HEAP_SIZE (0x08000000-0x00100000-0x00001000)
+ #else
+ #if defined(FIX_HW_BRN_26915)
+ #define SGX_CGBUFFER_HEAP_BASE 0x00100000
+ #define SGX_CGBUFFER_HEAP_SIZE (0x08000000-0x00100000-0x00001000)
+ #endif
#endif
#if defined(SUPPORT_SGX_GENERAL_MAPPING_HEAP)
#define SGX_PDSPIXEL_CODEDATA_HEAP_BASE 0xF6000000
#define SGX_PDSPIXEL_CODEDATA_HEAP_SIZE (0x02000000-0x00001000)
- #define SGX_PDSVERTEX_CODEDATA_HEAP_BASE 0xF8000000
- #define SGX_PDSVERTEX_CODEDATA_HEAP_SIZE (0x01E00000-0x00001000)
-
- #define SGX_KERNEL_CODE_HEAP_BASE 0xF9E00000
+ #define SGX_KERNEL_CODE_HEAP_BASE 0xF8000000
#define SGX_KERNEL_CODE_HEAP_SIZE (0x00080000-0x00001000)
-
- #define SGX_RESERVED_CODE_HEAP_BASE 0xF9F00000
- #define SGX_RESERVED_CODE_HEAP_SIZE (0x00080000-0x00001000)
+ #define SGX_PDSVERTEX_CODEDATA_HEAP_BASE 0xF8400000
+ #define SGX_PDSVERTEX_CODEDATA_HEAP_SIZE (0x01C00000-0x00001000)
#define SGX_KERNEL_DATA_HEAP_BASE 0xFA000000
#define SGX_KERNEL_DATA_HEAP_SIZE (0x05000000-0x00001000)
#define SGX_PIXELSHADER_HEAP_BASE 0xFF000000
#define SGX_PIXELSHADER_HEAP_SIZE (0x00500000-0x00001000)
- #define SGX_VERTEXSHADER_HEAP_BASE 0xFF500000
+ #define SGX_VERTEXSHADER_HEAP_BASE 0xFF800000
#define SGX_VERTEXSHADER_HEAP_SIZE (0x00200000-0x00001000)
#endif
#define SGX_GENERAL_HEAP_BASE 0x01800000
- #define SGX_GENERAL_HEAP_SIZE (0x06C00000-0x00001000)
+ #define SGX_GENERAL_HEAP_SIZE (0x07000000-0x00001000)
- #define SGX_3DPARAMETERS_HEAP_BASE 0x08400000
+ #define SGX_3DPARAMETERS_HEAP_BASE 0x08800000
#define SGX_3DPARAMETERS_HEAP_SIZE (0x04000000-0x00001000)
- #define SGX_TADATA_HEAP_BASE 0x0C400000
+ #define SGX_TADATA_HEAP_BASE 0x0C800000
#define SGX_TADATA_HEAP_SIZE (0x01000000-0x00001000)
- #define SGX_SYNCINFO_HEAP_BASE 0x0D400000
+ #define SGX_SYNCINFO_HEAP_BASE 0x0D800000
#define SGX_SYNCINFO_HEAP_SIZE (0x00400000-0x00001000)
- #define SGX_PDSPIXEL_CODEDATA_HEAP_BASE 0x0D800000
+ #define SGX_PDSPIXEL_CODEDATA_HEAP_BASE 0x0DC00000
#define SGX_PDSPIXEL_CODEDATA_HEAP_SIZE (0x00800000-0x00001000)
- #define SGX_PDSVERTEX_CODEDATA_HEAP_BASE 0x0E000000
- #define SGX_PDSVERTEX_CODEDATA_HEAP_SIZE (0x00800000-0x00001000)
-
-
- #define SGX_RESERVED_CODE_HEAP_BASE 0x0E800000
- #define SGX_RESERVED_CODE_HEAP_SIZE (0x00080000-0x00001000)
-
- #define SGX_KERNEL_CODE_HEAP_BASE 0x0EC00000
+ #define SGX_KERNEL_CODE_HEAP_BASE 0x0E400000
#define SGX_KERNEL_CODE_HEAP_SIZE (0x00080000-0x00001000)
+ #define SGX_PDSVERTEX_CODEDATA_HEAP_BASE 0x0E800000
+ #define SGX_PDSVERTEX_CODEDATA_HEAP_SIZE (0x00800000-0x00001000)
+
#define SGX_KERNEL_DATA_HEAP_BASE 0x0F000000
#define SGX_KERNEL_DATA_HEAP_SIZE (0x00400000-0x00001000)
IMG_UINT32 ui32CacheControl;
+ IMG_UINT32 ui32ClientBuildOptions;
+
+
+ SGX_MISCINFO_STRUCT_SIZES sSGXStructSizes;
+
+
IMG_VOID *pvMMUContextList;
#if defined(SGX_FEATURE_SPM_MODE_0)
psDevInfo->psKernelTmpDPMStateMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelTmpDPMStateMemInfo;
#endif
-#if 0
+
psDevInfo->ui32ClientBuildOptions = psInitInfo->ui32ClientBuildOptions;
psDevInfo->sSGXStructSizes = psInitInfo->sSGXStructSizes;
-#endif
+
eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
- //OSMemCopy(psDevInfo->aui32HostKickAddr, psInitInfo->aui32HostKickAddr,
- // SGXMKIF_CMD_MAX * sizeof(psDevInfo->aui32HostKickAddr[0]));
- memset(psDevInfo->aui32HostKickAddr, 0,
+ OSMemCopy(psDevInfo->aui32HostKickAddr, psInitInfo->aui32HostKickAddr,
SGXMKIF_CMD_MAX * sizeof(psDevInfo->aui32HostKickAddr[0]));
- psDevInfo->aui32HostKickAddr[SGXMKIF_CMD_TA] =
- psDevInfo->aui32HostKickAddr[SGXMKIF_CMD_TRANSFER] =
- psDevInfo->aui32HostKickAddr[SGXMKIF_CMD_2D] =
- psDevInfo->aui32HostKickAddr[SGXMKIF_CMD_POWER] =
- //psDevInfo->aui32HostKickAddr[SGXMKIF_CMD_CLEANUP] =
- psDevInfo->aui32HostKickAddr[SGXMKIF_CMD_PROCESS_QUEUES] = psInitInfo->ui32HostKickAddress;
- psDevInfo->aui32HostKickAddr[SGXMKIF_CMD_GETMISCINFO] = psInitInfo->ui32GetMiscInfoAddress;
psDevInfo->bForcePTOff = IMG_FALSE;
PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo)
{
PVRSRV_ERROR eError;
-#if 0
PVRSRV_KERNEL_MEM_INFO *psSGXHostCtlMemInfo = psDevInfo->psKernelSGXHostCtlMemInfo;
SGXMKIF_HOST_CTL *psSGXHostCtl = psSGXHostCtlMemInfo->pvLinAddrKM;
-#endif
#if defined(PDUMP)
static IMG_BOOL bFirstTime = IMG_TRUE;
#endif
PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "End of SGX initialisation script part 2\n");
if(cpu_is_omap3630())
- OSWriteHWReg(psDevInfo->pvRegsBaseKM, 0xFF08, 0x80000000);//OCP Bypass mode
-
-{
- extern IMG_VOID SGXStartTimer(PVRSRV_SGXDEV_INFO *psDevInfo);
- SGXStartTimer(psDevInfo);
-}
+ OSWriteHWReg(psDevInfo->pvRegsBaseKM, 0xFF08, 0x80000000);
-#if 0
psSGXHostCtl->ui32InitStatus = 0;
-#endif
#if defined(PDUMP)
PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
"Reset the SGX microkernel initialisation status\n");
}
#endif
-#if 0 // !defined(NO_HARDWARE)
+#if !defined(NO_HARDWARE)
if (PollForValueKM(&psSGXHostCtl->ui32InitStatus,
PPVRSRV_KERNEL_MEM_INFO psMemInfo;
PVRSRV_SGX_MISCINFO_INFO *psSGXMiscInfoInt;
PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
-#if 0
SGX_MISCINFO_STRUCT_SIZES *psSGXStructSizes;
IMG_BOOL bStructSizesFailed;
const IMG_UINT32 ui32NumCoreExceptions = sizeof(aui32CoreRevExceptions) / (2*sizeof(IMG_UINT32));
IMG_UINT i;
#endif
-#endif
if(psDeviceNode->sDevId.eDeviceType != PVRSRV_DEVICE_TYPE_SGX)
psDevInfo = psDeviceNode->pvDevice;
-#if 0
+
ui32BuildOptions = (SGX_BUILD_OPTIONS);
if (ui32BuildOptions != psDevInfo->ui32ClientBuildOptions)
{
{
PVR_DPF((PVR_DBG_MESSAGE, "SGXInit: Client-side and KM driver build options match. [ OK ]"));
}
-#endif
+
#if !defined (NO_HARDWARE)
psMemInfo = psDevInfo->psKernelSGXMiscMemInfo;
PVRVERSION_BUILD, psSGXFeatures->ui32DDKBuild));
}
-#if 0
+
if (psSGXFeatures->ui32CoreRevSW == 0)
{
}
}
}
-#endif
-#if 0
+
+
psSGXStructSizes = &((PVRSRV_SGX_MISCINFO_INFO*)(psMemInfo->pvLinAddrKM))->sSGXStructSizes;
bStructSizesFailed = IMG_FALSE;
{
PVR_DPF((PVR_DBG_MESSAGE, "SGXInit: SGXMKIF structure sizes match. [ OK ]"));
}
-#endif
+
ui32BuildOptions = psSGXFeatures->ui32BuildOptions;
if (ui32BuildOptions != (SGX_BUILD_OPTIONS))
SGXMKIF_COMMAND sCommandData;
PVRSRV_SGX_MISCINFO_INFO *psSGXMiscInfoInt;
PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
-#if 0
SGX_MISCINFO_STRUCT_SIZES *psSGXStructSizes;
-#endif
+
PPVRSRV_KERNEL_MEM_INFO psMemInfo = psDevInfo->psKernelSGXMiscMemInfo;
if (! psMemInfo->pvLinAddrKM)
}
psSGXMiscInfoInt = psMemInfo->pvLinAddrKM;
psSGXFeatures = &psSGXMiscInfoInt->sSGXFeatures;
-#if 0
psSGXStructSizes = &psSGXMiscInfoInt->sSGXStructSizes;
-#endif
+
psSGXMiscInfoInt->ui32MiscInfoFlags &= ~PVRSRV_USSE_MISCINFO_READY;
OSMemSet(psSGXFeatures, 0, sizeof(*psSGXFeatures));
-#if 0
OSMemSet(psSGXStructSizes, 0, sizeof(*psSGXStructSizes));
-#endif
sCommandData.ui32Data[1] = psMemInfo->sDevVAddr.uiAddr;
psDiffs->ui32Time[0] = OSClockus();
psDiffs->ui32Time[1] = psDevInfo->psSGXHostCtl->ui32TimeWraps;
-#if 0
psDiffs->ui32Time[2] = ui32rval;
-#endif
+
psDiffs->ui32Marker[0] = psDevInfo->ui32KickTACounter;
psDiffs->ui32Marker[1] = psDevInfo->ui32KickTARenderCounter;
}
MAKEUNIQUETAG(psHWDstSyncListMemInfo));
}
#endif
-#if 0
+
for (i=0; i<ui32NumDstSyncs; i++)
-#endif
{
-#if 0
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->pahDstSyncHandles[i];
-#else
- psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->sDstSyncHandle;
- i = 0;
-#endif
+
if (psSyncInfo)
{
psHWDeviceSyncList->asSyncData[i].sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr;
-#if 0
+
psTACmd->ui32CtrlFlags |= SGXMKIF_CMDTA_CTRLFLAGS_READY;
-#endif
+
#if defined(PDUMP)
if (PDumpIsCaptureFrameKM())
{
#endif
eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_TA, &psCCBKick->sCommand, KERNEL_ID, 0);
-// eError = SGXScheduleCCBCommandKM(hDevHandle, psCCBKick->eCommand, &psCCBKick->sCommand, KERNEL_ID, 0);
if (eError == PVRSRV_ERROR_RETRY)
{
if (psCCBKick->bFirstKickOrResume && psCCBKick->ui32NumDstSyncObjects > 0)
{
-#if 0
for (i=0; i < psCCBKick->ui32NumDstSyncObjects; i++)
-#endif
{
-#if 0
-
+
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->pahDstSyncHandles[i];
-#else
- psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->sDstSyncHandle;
-#endif
if (psSyncInfo)
{
psSyncInfo->psSyncData->ui32WriteOpsPending--;
psDevInfo->ui32CoreClockSpeed = psSGXTimingInfo->ui32CoreClockSpeed;
psDevInfo->ui32uKernelTimerClock = psSGXTimingInfo->ui32CoreClockSpeed / psSGXTimingInfo->ui32uKernelFreq;
-#if 0
+
psDevInfo->psSGXHostCtl->ui32uKernelTimerClock = psDevInfo->ui32uKernelTimerClock;
-#endif
#if defined(PDUMP)
PDUMPCOMMENT("Host Control - Microkernel clock");
PDUMPMEM(IMG_NULL, psDevInfo->psKernelSGXHostCtlMemInfo,
}
-IMG_VOID SGXStartTimer(PVRSRV_SGXDEV_INFO *psDevInfo)
+static IMG_VOID SGXStartTimer(PVRSRV_SGXDEV_INFO *psDevInfo)
{
- IMG_UINT32 ui32RegVal;
-
- ui32RegVal = EUR_CR_EVENT_TIMER_ENABLE_MASK | psDevInfo->ui32uKernelTimerClock;
- OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_TIMER, ui32RegVal);
- PDUMPREGWITHFLAGS(EUR_CR_EVENT_TIMER, ui32RegVal, PDUMP_FLAGS_CONTINUOUS);
-
#if defined(SUPPORT_HW_RECOVERY)
- if (1)
+ PVRSRV_ERROR eError;
+
+ eError = OSEnableTimer(psDevInfo->hTimer);
+ if (eError != PVRSRV_OK)
{
- PVRSRV_ERROR eError;
-
- eError = OSEnableTimer(psDevInfo->hTimer);
- if (eError != PVRSRV_OK)
- {
- PVR_DPF((PVR_DBG_ERROR,"SGXStartTimer : Failed to enable host timer"));
- }
+ PVR_DPF((PVR_DBG_ERROR,"SGXStartTimer : Failed to enable host timer"));
}
+ #else
+ PVR_UNREFERENCED_PARAMETER(psDevInfo);
#endif
}
SGXMKIF_COMMAND sCommand = {0};
-#if 0
+
sCommand.ui32Data[1] = PVRSRV_POWERCMD_RESUME;
eError = SGXScheduleCCBCommand(psDevInfo, SGXMKIF_CMD_POWER, &sCommand, ISR_ID, 0);
-#else
- eError = SGXScheduleCCBCommand(psDevInfo, SGXMKIF_CMD_PROCESS_QUEUES, &sCommand, ISR_ID, 0);
-#endif
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXPostPowerState failed to schedule CCB command: %lu", eError));
#include <stdio.h>
#endif
-#define PVRSRV_USSE_EDM_RESMAN_CLEANUP_INVALPD 0x20UL
-#define PVRSRV_USSE_EDM_RESMAN_CLEANUP_INVALPT 0x40UL
-#define PVRSRV_USSE_EDM_RESMAN_CLEANUP_COMPLETE 0x80UL
-
#if defined(SYS_CUSTOM_POWERDOWN)
PVRSRV_ERROR SysPowerDownMISR(PVRSRV_DEVICE_NODE * psDeviceNode, IMG_UINT32 ui32CallerID);
}
#endif
- psSGXCommand->ui32Data[0] = eCmdType;
psSGXCommand->ui32ServiceAddress = psDevInfo->aui32HostKickAddr[eCmdType];
#if defined(PDUMP)
}
else
{
-#if 1
- if (psSGXDevInfo->ui32CacheControl & SGX_BIF_INVALIDATE_PDCACHE)
- {
- psSGXHostCtl->ui32ResManFlags |= PVRSRV_USSE_EDM_RESMAN_CLEANUP_INVALPD;
- psSGXDevInfo->ui32CacheControl ^= SGX_BIF_INVALIDATE_PDCACHE;
- }
- if (psSGXDevInfo->ui32CacheControl & SGX_BIF_INVALIDATE_PTCACHE)
- {
- psSGXHostCtl->ui32ResManFlags |= PVRSRV_USSE_EDM_RESMAN_CLEANUP_INVALPT;
- psSGXDevInfo->ui32CacheControl ^= SGX_BIF_INVALIDATE_PTCACHE;
- }
-
- if(psHWDataDevVAddr == IMG_NULL)
- {
- psSGXHostCtl->sResManCleanupData.uiAddr = 0;
- }
- else
- {
-
- psSGXHostCtl->sResManCleanupData.uiAddr = psHWDataDevVAddr->uiAddr;
- }
-
-
- psSGXHostCtl->ui32ResManFlags |= 1 << (ui32CleanupType - 1);
-
- eError = SGXScheduleProcessQueuesKM(psDeviceNode);
-
-
- #if !defined(NO_HARDWARE)
- if(PollForValueKM ((volatile IMG_UINT32 *)(&psSGXHostCtl->ui32ResManFlags),
- PVRSRV_USSE_EDM_RESMAN_CLEANUP_COMPLETE,
- PVRSRV_USSE_EDM_RESMAN_CLEANUP_COMPLETE,
- MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT) != PVRSRV_OK)
- {
- PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Wait for uKernel to clean up failed"));
- PVR_DBG_BREAK;
- }
- #endif
-
- psSGXHostCtl->ui32ResManFlags &= ~(PVRSRV_USSE_EDM_RESMAN_CLEANUP_COMPLETE);
-#else
SGXMKIF_COMMAND sCommand = {0};
PDUMPCOMMENTWITHFLAGS(0, "Request ukernel resouce clean-up");
psSGXHostCtl->ui32CleanupStatus &= ~(PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE);
PDUMPMEM(IMG_NULL, psSGXHostCtlMemInfo, offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus), sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psSGXHostCtlMemInfo));
-#endif
}
}
git.openpandora.org / sgx.git / commitdiff