net: sh_eth: arm: renesas: README: Drop CFG_SH_ETHER_CACHE_*

Drop CFG_SH_ETHER_CACHE_WRITEBACK and CFG_SH_ETHER_CACHE_INVALIDATE,
which are now always enabled in the sh_eth driver, because those cache
operations are always available. On architectures which do not implement
cache operations yet, cache operations have to be implemented first.

CFG_SH_ETHER_ALIGNE_SIZE now set as SH_ETHER_ALIGN_SIZE in sh_eth.h
based on architecture and no longer configured on board level.

Remove CFG_SH_ETHER_CACHE_WRITEBACK configuration option from README.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/README b/README
index 8f8f4b8..7acf395 100644 (file)
--- a/README
+++ b/README
@@ -382,9 +382,6 @@ The following options need to be configured:
                        CFG_SH_ETHER_PHY_ADDR
                        Define the ETH PHY's address
 
-                       CFG_SH_ETHER_CACHE_WRITEBACK
-                       If this option is set, the driver enables cache flush.
-
 - TPM Support:
                CONFIG_TPM
                Support TPM devices.

diff --git a/include/configs/alt.h b/include/configs/alt.h
index 52b8c95..987fd25 100644 (file)
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -23,9 +23,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 

diff --git a/include/configs/condor.h b/include/configs/condor.h
index ecaf58e..b2d66c7 100644 (file)
--- a/include/configs/condor.h
+++ b/include/configs/condor.h
@@ -16,9 +16,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 /* XTAL_CLK : 33.33MHz */

diff --git a/include/configs/gose.h b/include/configs/gose.h
index 323977e..acef925 100644 (file)
--- a/include/configs/gose.h
+++ b/include/configs/gose.h
@@ -22,9 +22,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 

diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index 67ad833..9a7eef5 100644 (file)
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h
@@ -19,8 +19,5 @@
 /* Network interface */
 #define CFG_SH_ETHER_PHY_ADDR  0
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 #endif /* __GRPEACH_H */

diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index 11f637d..13d2127 100644 (file)
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -22,9 +22,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 

diff --git a/include/configs/lager.h b/include/configs/lager.h
index aaf4a4a..d76f003 100644 (file)
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -23,9 +23,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 

diff --git a/include/configs/porter.h b/include/configs/porter.h
index ff99c3f..eaf5d31 100644 (file)
--- a/include/configs/porter.h
+++ b/include/configs/porter.h
@@ -24,9 +24,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 

diff --git a/include/configs/silk.h b/include/configs/silk.h
index 20d18aa..4ef7028 100644 (file)
--- a/include/configs/silk.h
+++ b/include/configs/silk.h
@@ -24,9 +24,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 

diff --git a/include/configs/stout.h b/include/configs/stout.h
index 454d8ca..cb544de 100644 (file)
--- a/include/configs/stout.h
+++ b/include/configs/stout.h
@@ -28,9 +28,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 

diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h
index e16a289..a8d1641 100644 (file)
--- a/include/configs/v3hsk.h
+++ b/include/configs/v3hsk.h
@@ -17,9 +17,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x0
 #define CFG_SH_ETHER_PHY_MODE  PHY_INTERFACE_MODE_RGMII_ID
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 /* XTAL_CLK : 33.33MHz */