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[MIPS] Fix pipeline hazard.
authorRalf Baechle <ralf@linux-mips.org>
Tue, 20 Mar 2007 13:56:50 +0000 (13:56 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Sat, 24 Mar 2007 17:01:49 +0000 (17:01 +0000)
In the the sequence:
        ei
        ..
        mfc0    $x, $status

the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the
kernel code because we knew this was a safe thing to do on all R2 silicon
so far but new silicon is changing this.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

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