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drm/i915: Program correct m n tu register for Valleyview
authorVijay Purushothaman <vijay.a.purushothaman@intel.com>
Thu, 27 Sep 2012 13:43:04 +0000 (19:13 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 28 Sep 2012 14:49:53 +0000 (16:49 +0200)
m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

No differences found
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