ARM: uniphier: de-couple SC macros into base address and offset

The SC_* macros represent the address of SysCtrl registers.
For a planned new SoC, its base address will be changed.

Turn the SC_* macros into the offset from the base address.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

diff --git a/arch/arm/mach-uniphier/arm32/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S
index c155246..3fed798 100644 (file)
--- a/arch/arm/mach-uniphier/arm32/debug_ll.S
+++ b/arch/arm/mach-uniphier/arm32/debug_ll.S
@@ -63,7 +63,7 @@ ld4_end:
        mov             r1, #1
        str             r1, [r0]
 
-       ldr             r0, =SC_CLKCTRL
+       ldr             r0, =(SC_BASE + SC_CLKCTRL)
        ldr             r1, [r0]
        orr             r1, r1, #SC_CLKCTRL_CEN_PERI
        str             r1, [r0]
@@ -104,7 +104,7 @@ sld8_end:
        mov             r1, #1
        str             r1, [r0]
 
-       ldr             r0, =SC_CLKCTRL
+       ldr             r0, =(SC_BASE + SC_CLKCTRL)
        ldr             r1, [r0]
        orr             r1, r1, #SC_CLKCTRL_CEN_PERI
        str             r1, [r0]
@@ -129,7 +129,7 @@ pro5_end:
        sg_set_pinsel   113, 8, 8, 4, r0, r1    @ TXD2 -> TXD2
        sg_set_pinsel   219, 8, 8, 4, r0, r1    @ TXD3 -> TXD3
 
-       ldr             r0, =SC_CLKCTRL
+       ldr             r0, =(SC_BASE + SC_CLKCTRL)
        ldr             r1, [r0]
        orr             r1, r1, #SC_CLKCTRL_CEN_PERI
        str             r1, [r0]
@@ -153,7 +153,7 @@ pxs2_end:
        sg_set_pinsel   115, 0, 8, 4, r0, r1    @ TXD1 -> TXD1
        sg_set_pinsel   113, 2, 8, 4, r0, r1    @ SBO0 -> TXD2
 
-       ldr             r0, =SC_CLKCTRL
+       ldr             r0, =(SC_BASE + SC_CLKCTRL)
        ldr             r1, [r0]
        orr             r1, r1, #SC_CLKCTRL_CEN_PERI
        str             r1, [r0]

diff --git a/arch/arm/mach-uniphier/clk/clk-dram-ld4.c b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c
index 39cde44..c796d36 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-dram-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c
@@ -16,14 +16,14 @@ void uniphier_ld4_dram_clk_init(void)
        u32 tmp;
 
        /* deassert reset */
-       tmp = readl(SC_RSTCTRL);
+       tmp = readl(sc_base + SC_RSTCTRL);
        tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
-       writel(tmp, SC_RSTCTRL);
-       readl(SC_RSTCTRL); /* dummy read */
+       writel(tmp, sc_base + SC_RSTCTRL);
+       readl(sc_base + SC_RSTCTRL); /* dummy read */
 
        /* provide clocks */
-       tmp = readl(SC_CLKCTRL);
+       tmp = readl(sc_base + SC_CLKCTRL);
        tmp |= SC_CLKCTRL_CEN_UMC;
-       writel(tmp, SC_CLKCTRL);
-       readl(SC_CLKCTRL); /* dummy read */
+       writel(tmp, sc_base + SC_CLKCTRL);
+       readl(sc_base + SC_CLKCTRL); /* dummy read */
 }

diff --git a/arch/arm/mach-uniphier/clk/clk-dram-pro5.c b/arch/arm/mach-uniphier/clk/clk-dram-pro5.c
index 7674ceb..808d1eb 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-dram-pro5.c
+++ b/arch/arm/mach-uniphier/clk/clk-dram-pro5.c
@@ -18,17 +18,17 @@ void uniphier_pro5_dram_clk_init(void)
         * UMCA1, UMC31: Ch0 (WIO1)
         * UMCA0, UMC30: Ch0 (WIO0)
         */
-       tmp = readl(SC_RSTCTRL4);
+       tmp = readl(sc_base + SC_RSTCTRL4);
        tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
               SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
               SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
-       writel(tmp, SC_RSTCTRL4);
-       readl(SC_RSTCTRL4); /* dummy read */
+       writel(tmp, sc_base + SC_RSTCTRL4);
+       readl(sc_base + SC_RSTCTRL4); /* dummy read */
 
        /* provide clocks */
-       tmp = readl(SC_CLKCTRL4);
+       tmp = readl(sc_base + SC_CLKCTRL4);
        tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
               SC_CLKCTRL4_CEN_UMC0;
-       writel(tmp, SC_CLKCTRL4);
-       readl(SC_CLKCTRL4); /* dummy read */
+       writel(tmp, sc_base + SC_CLKCTRL4);
+       readl(sc_base + SC_CLKCTRL4); /* dummy read */
 }

diff --git a/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c b/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c
index ad4e83a..b78bd01 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c
+++ b/arch/arm/mach-uniphier/clk/clk-dram-pxs2.c
@@ -15,18 +15,18 @@ void uniphier_pxs2_dram_clk_init(void)
        u32 tmp;
 
        /* deassert reset */
-       tmp = readl(SC_RSTCTRL4);
+       tmp = readl(sc_base + SC_RSTCTRL4);
        tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
               SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
               SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 |
               SC_RSTCTRL4_NRST_UMC30;
-       writel(tmp, SC_RSTCTRL4);
-       readl(SC_RSTCTRL4); /* dummy read */
+       writel(tmp, sc_base + SC_RSTCTRL4);
+       readl(sc_base + SC_RSTCTRL4); /* dummy read */
 
        /* provide clocks */
-       tmp = readl(SC_CLKCTRL4);
+       tmp = readl(sc_base + SC_CLKCTRL4);
        tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 |
               SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0;
-       writel(tmp, SC_CLKCTRL4);
-       readl(SC_CLKCTRL4); /* dummy read */
+       writel(tmp, sc_base + SC_CLKCTRL4);
+       readl(sc_base + SC_CLKCTRL4); /* dummy read */
 }

diff --git a/arch/arm/mach-uniphier/clk/clk-early-ld4.c b/arch/arm/mach-uniphier/clk/clk-early-ld4.c
index eb36a9e..f32f78d 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-early-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-early-ld4.c
@@ -17,14 +17,14 @@ void uniphier_ld4_early_clk_init(void)
 
        /* deassert reset */
        if (spl_boot_device() != BOOT_DEVICE_NAND) {
-               tmp = readl(SC_RSTCTRL);
+               tmp = readl(sc_base + SC_RSTCTRL);
                tmp &= ~SC_RSTCTRL_NRST_NAND;
-               writel(tmp, SC_RSTCTRL);
+               writel(tmp, sc_base + SC_RSTCTRL);
        };
 
        /* provide clocks */
-       tmp = readl(SC_CLKCTRL);
+       tmp = readl(sc_base + SC_CLKCTRL);
        tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
-       writel(tmp, SC_CLKCTRL);
-       readl(SC_CLKCTRL); /* dummy read */
+       writel(tmp, sc_base + SC_CLKCTRL);
+       readl(sc_base + SC_CLKCTRL); /* dummy read */
 }

diff --git a/arch/arm/mach-uniphier/clk/clk-ld20.c b/arch/arm/mach-uniphier/clk/clk-ld20.c
index 02a14dd..397b2d7 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-ld20.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld20.c
@@ -15,13 +15,13 @@ void uniphier_ld20_clk_init(void)
 {
        u32 tmp;
 
-       tmp = readl(SC_RSTCTRL6);
+       tmp = readl(sc_base + SC_RSTCTRL6);
        tmp |= BIT(8);                  /* Mali */
-       writel(tmp, SC_RSTCTRL6);
+       writel(tmp, sc_base + SC_RSTCTRL6);
 
-       tmp = readl(SC_CLKCTRL6);
+       tmp = readl(sc_base + SC_CLKCTRL6);
        tmp |= BIT(8);                  /* Mali */
-       writel(tmp, SC_CLKCTRL6);
+       writel(tmp, sc_base + SC_CLKCTRL6);
 
        /* TODO: use "mmc-pwrseq-emmc" */
        writel(1, SDCTRL_EMMC_HW_RESET);

diff --git a/arch/arm/mach-uniphier/clk/clk-ld4.c b/arch/arm/mach-uniphier/clk/clk-ld4.c
index 9c88cde..0393942 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-ld4.c
@@ -15,18 +15,18 @@ void uniphier_ld4_clk_init(void)
        u32 tmp;
 
        /* deassert reset */
-       tmp = readl(SC_RSTCTRL);
+       tmp = readl(sc_base + SC_RSTCTRL);
 #ifdef CONFIG_NAND_DENALI
        tmp |= SC_RSTCTRL_NRST_NAND;
 #endif
-       writel(tmp, SC_RSTCTRL);
-       readl(SC_RSTCTRL); /* dummy read */
+       writel(tmp, sc_base + SC_RSTCTRL);
+       readl(sc_base + SC_RSTCTRL); /* dummy read */
 
        /* provide clocks */
-       tmp = readl(SC_CLKCTRL);
+       tmp = readl(sc_base + SC_CLKCTRL);
 #ifdef CONFIG_NAND_DENALI
        tmp |= SC_CLKCTRL_CEN_NAND;
 #endif
-       writel(tmp, SC_CLKCTRL);
-       readl(SC_CLKCTRL); /* dummy read */
+       writel(tmp, sc_base + SC_CLKCTRL);
+       readl(sc_base + SC_CLKCTRL); /* dummy read */
 }

diff --git a/arch/arm/mach-uniphier/clk/clk-pro4.c b/arch/arm/mach-uniphier/clk/clk-pro4.c
index 32d44c0..2b364dc 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-pro4.c
+++ b/arch/arm/mach-uniphier/clk/clk-pro4.c
@@ -15,7 +15,7 @@ void uniphier_pro4_clk_init(void)
        u32 tmp;
 
        /* deassert reset */
-       tmp = readl(SC_RSTCTRL);
+       tmp = readl(sc_base + SC_RSTCTRL);
 #ifdef CONFIG_USB_DWC3_UNIPHIER
        tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
                SC_RSTCTRL_NRST_GIO;
@@ -23,18 +23,18 @@ void uniphier_pro4_clk_init(void)
 #ifdef CONFIG_NAND_DENALI
        tmp |= SC_RSTCTRL_NRST_NAND;
 #endif
-       writel(tmp, SC_RSTCTRL);
-       readl(SC_RSTCTRL); /* dummy read */
+       writel(tmp, sc_base + SC_RSTCTRL);
+       readl(sc_base + SC_RSTCTRL); /* dummy read */
 
 #ifdef CONFIG_USB_DWC3_UNIPHIER
-       tmp = readl(SC_RSTCTRL2);
+       tmp = readl(sc_base + SC_RSTCTRL2);
        tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
-       writel(tmp, SC_RSTCTRL2);
-       readl(SC_RSTCTRL2); /* dummy read */
+       writel(tmp, sc_base + SC_RSTCTRL2);
+       readl(sc_base + SC_RSTCTRL2); /* dummy read */
 #endif
 
        /* provide clocks */
-       tmp = readl(SC_CLKCTRL);
+       tmp = readl(sc_base + SC_CLKCTRL);
 #ifdef CONFIG_USB_DWC3_UNIPHIER
        tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
                SC_CLKCTRL_CEN_GIO;
@@ -42,6 +42,6 @@ void uniphier_pro4_clk_init(void)
 #ifdef CONFIG_NAND_DENALI
        tmp |= SC_CLKCTRL_CEN_NAND;
 #endif
-       writel(tmp, SC_CLKCTRL);
-       readl(SC_CLKCTRL); /* dummy read */
+       writel(tmp, sc_base + SC_CLKCTRL);
+       readl(sc_base + SC_CLKCTRL); /* dummy read */
 }

diff --git a/arch/arm/mach-uniphier/clk/clk-pro5.c b/arch/arm/mach-uniphier/clk/clk-pro5.c
index 338d73d..874964b 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-pro5.c
+++ b/arch/arm/mach-uniphier/clk/clk-pro5.c
@@ -13,25 +13,25 @@ void uniphier_pro5_clk_init(void)
        u32 tmp;
 
        /* deassert reset */
-       tmp = readl(SC_RSTCTRL);
+       tmp = readl(sc_base + SC_RSTCTRL);
 #ifdef CONFIG_USB_DWC3_UNIPHIER
        tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
 #endif
 #ifdef CONFIG_NAND_DENALI
        tmp |= SC_RSTCTRL_NRST_NAND;
 #endif
-       writel(tmp, SC_RSTCTRL);
-       readl(SC_RSTCTRL); /* dummy read */
+       writel(tmp, sc_base + SC_RSTCTRL);
+       readl(sc_base + SC_RSTCTRL); /* dummy read */
 
 #ifdef CONFIG_USB_DWC3_UNIPHIER
-       tmp = readl(SC_RSTCTRL2);
+       tmp = readl(sc_base + SC_RSTCTRL2);
        tmp |= SC_RSTCTRL2_NRST_USB3B1;
-       writel(tmp, SC_RSTCTRL2);
-       readl(SC_RSTCTRL2); /* dummy read */
+       writel(tmp, sc_base + SC_RSTCTRL2);
+       readl(sc_base + SC_RSTCTRL2); /* dummy read */
 #endif
 
        /* provide clocks */
-       tmp = readl(SC_CLKCTRL);
+       tmp = readl(sc_base + SC_CLKCTRL);
 #ifdef CONFIG_USB_DWC3_UNIPHIER
        tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
                SC_CLKCTRL_CEN_GIO;
@@ -39,6 +39,6 @@ void uniphier_pro5_clk_init(void)
 #ifdef CONFIG_NAND_DENALI
        tmp |= SC_CLKCTRL_CEN_NAND;
 #endif
-       writel(tmp, SC_CLKCTRL);
-       readl(SC_CLKCTRL); /* dummy read */
+       writel(tmp, sc_base + SC_CLKCTRL);
+       readl(sc_base + SC_CLKCTRL); /* dummy read */
 }

diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c
index afa12fa..8cb4f87 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-pxs2.c
+++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c
@@ -14,29 +14,29 @@ void uniphier_pxs2_clk_init(void)
        u32 tmp;
 
        /* deassert reset */
-       tmp = readl(SC_RSTCTRL);
+       tmp = readl(sc_base + SC_RSTCTRL);
 #ifdef CONFIG_USB_DWC3_UNIPHIER
        tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
 #endif
 #ifdef CONFIG_NAND_DENALI
        tmp |= SC_RSTCTRL_NRST_NAND;
 #endif
-       writel(tmp, SC_RSTCTRL);
-       readl(SC_RSTCTRL); /* dummy read */
+       writel(tmp, sc_base + SC_RSTCTRL);
+       readl(sc_base + SC_RSTCTRL); /* dummy read */
 
 #ifdef CONFIG_USB_DWC3_UNIPHIER
-       tmp = readl(SC_RSTCTRL2);
+       tmp = readl(sc_base + SC_RSTCTRL2);
        tmp |= SC_RSTCTRL2_NRST_USB3B1;
-       writel(tmp, SC_RSTCTRL2);
-       readl(SC_RSTCTRL2); /* dummy read */
+       writel(tmp, sc_base + SC_RSTCTRL2);
+       readl(sc_base + SC_RSTCTRL2); /* dummy read */
 
-       tmp = readl(SC_RSTCTRL6);
+       tmp = readl(sc_base + SC_RSTCTRL6);
        tmp |= 0x37;
-       writel(tmp, SC_RSTCTRL6);
+       writel(tmp, sc_base + SC_RSTCTRL6);
 #endif
 
        /* provide clocks */
-       tmp = readl(SC_CLKCTRL);
+       tmp = readl(sc_base + SC_CLKCTRL);
 #ifdef CONFIG_USB_DWC3_UNIPHIER
        tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
                SC_CLKCTRL_CEN_GIO;
@@ -44,6 +44,6 @@ void uniphier_pxs2_clk_init(void)
 #ifdef CONFIG_NAND_DENALI
        tmp |= SC_CLKCTRL_CEN_NAND;
 #endif
-       writel(tmp, SC_CLKCTRL);
-       readl(SC_CLKCTRL); /* dummy read */
+       writel(tmp, sc_base + SC_CLKCTRL);
+       readl(sc_base + SC_CLKCTRL); /* dummy read */
 }

diff --git a/arch/arm/mach-uniphier/clk/clk-pxs3.c b/arch/arm/mach-uniphier/clk/clk-pxs3.c
index 73824e9..33b9c5b 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-pxs3.c
+++ b/arch/arm/mach-uniphier/clk/clk-pxs3.c
@@ -15,13 +15,13 @@ void uniphier_pxs3_clk_init(void)
 {
        u32 tmp;
 
-       tmp = readl(SC_RSTCTRL6);
+       tmp = readl(sc_base + SC_RSTCTRL6);
        tmp |= BIT(8);                  /* Mali */
-       writel(tmp, SC_RSTCTRL6);
+       writel(tmp, sc_base + SC_RSTCTRL6);
 
-       tmp = readl(SC_CLKCTRL6);
+       tmp = readl(sc_base + SC_CLKCTRL6);
        tmp |= BIT(8);                  /* Mali */
-       writel(tmp, SC_CLKCTRL6);
+       writel(tmp, sc_base + SC_CLKCTRL6);
 
        /* TODO: use "mmc-pwrseq-emmc" */
        writel(1, SDCTRL_EMMC_HW_RESET);

diff --git a/arch/arm/mach-uniphier/clk/dpll-ld4.c b/arch/arm/mach-uniphier/clk/dpll-ld4.c
index 4b9ec07..72fe8db 100644 (file)
--- a/arch/arm/mach-uniphier/clk/dpll-ld4.c
+++ b/arch/arm/mach-uniphier/clk/dpll-ld4.c
@@ -23,7 +23,7 @@ int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd)
         * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
         * to FOUT (DPLLCTRL.bit[29:20])
         */
-       tmp = readl(SC_DPLLCTRL);
+       tmp = readl(sc_base + SC_DPLLCTRL);
        tmp &= ~0x000f0000;
        switch (dram_freq) {
        case 1333:
@@ -42,11 +42,11 @@ int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd)
 #else
        tmp |= SC_DPLLCTRL_SSC_RATE;
 #endif
-       writel(tmp, SC_DPLLCTRL);
+       writel(tmp, sc_base + SC_DPLLCTRL);
 
-       tmp = readl(SC_DPLLCTRL2);
+       tmp = readl(sc_base + SC_DPLLCTRL2);
        tmp |= SC_DPLLCTRL2_NRSTDS;
-       writel(tmp, SC_DPLLCTRL2);
+       writel(tmp, sc_base + SC_DPLLCTRL2);
 
        /* Wait 500 usec until dpll gets stable */
        udelay(500);

diff --git a/arch/arm/mach-uniphier/clk/dpll-pro4.c b/arch/arm/mach-uniphier/clk/dpll-pro4.c
index 2965946..6259495 100644 (file)
--- a/arch/arm/mach-uniphier/clk/dpll-pro4.c
+++ b/arch/arm/mach-uniphier/clk/dpll-pro4.c
@@ -23,7 +23,7 @@ int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd)
         * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
         * to FOUT ( DPLLCTRL.bit[29:20] )
         */
-       tmp = readl(SC_DPLLCTRL);
+       tmp = readl(sc_base + SC_DPLLCTRL);
        tmp &= ~(0x000f0000);
        switch (dram_freq) {
        case 1333:
@@ -46,11 +46,11 @@ int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd)
 #else
        tmp |= 0x00008000;
 #endif
-       writel(tmp, SC_DPLLCTRL);
+       writel(tmp, sc_base + SC_DPLLCTRL);
 
-       tmp = readl(SC_DPLLCTRL2);
+       tmp = readl(sc_base + SC_DPLLCTRL2);
        tmp |= SC_DPLLCTRL2_NRSTDS;
-       writel(tmp, SC_DPLLCTRL2);
+       writel(tmp, sc_base + SC_DPLLCTRL2);
 
        /* Wait until dpll gets stable */
        udelay(500);

diff --git a/arch/arm/mach-uniphier/clk/dpll-sld8.c b/arch/arm/mach-uniphier/clk/dpll-sld8.c
index 1d7b752..1ac52d1 100644 (file)
--- a/arch/arm/mach-uniphier/clk/dpll-sld8.c
+++ b/arch/arm/mach-uniphier/clk/dpll-sld8.c
@@ -22,10 +22,10 @@ int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd)
         * [4]     ICPD_TEST    0x1
         * [3:0]   ICPD         0xb
         */
-       tmp = readl(SC_DPLLCTRL3);
+       tmp = readl(sc_base + SC_DPLLCTRL3);
        tmp &= ~0x00ff0717;
        tmp |= 0x00d0061b;
-       writel(tmp, SC_DPLLCTRL3);
+       writel(tmp, sc_base + SC_DPLLCTRL3);
 
        /*
         * Set DPLL SSC parameters for DPLLCTRL
@@ -33,14 +33,14 @@ int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd)
         * [29:20] SSC_UPCNT 132 (0x084)    132  (0x084)
         * [14:0]  SSC_dK    6335(0x18bf)   12710(0x31a6)
         */
-       tmp = readl(SC_DPLLCTRL);
+       tmp = readl(sc_base + SC_DPLLCTRL);
        tmp &= ~0x3ff07fff;
 #ifdef DPLL_SSC_RATE_1PER
        tmp |= 0x084018bf;
 #else
        tmp |= 0x084031a6;
 #endif
-       writel(tmp, SC_DPLLCTRL);
+       writel(tmp, sc_base + SC_DPLLCTRL);
 
        /*
         * Set DPLL SSC parameters for DPLLCTRL2
@@ -49,10 +49,10 @@ int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd)
         * [26:20]  SSC_M        79     (0x4f)
         * [19:0]   SSC_K        964689 (0xeb851)
         */
-       tmp = readl(SC_DPLLCTRL2);
+       tmp = readl(sc_base + SC_DPLLCTRL2);
        tmp &= ~0xefffffff;
        tmp |= 0x0cfeb851;
-       writel(tmp, SC_DPLLCTRL2);
+       writel(tmp, sc_base + SC_DPLLCTRL2);
 
        /* Wait 500 usec until dpll gets stable */
        udelay(500);

diff --git a/arch/arm/mach-uniphier/clk/dpll-tail.c b/arch/arm/mach-uniphier/clk/dpll-tail.c
index 7f434f6..6ba5a36 100644 (file)
--- a/arch/arm/mach-uniphier/clk/dpll-tail.c
+++ b/arch/arm/mach-uniphier/clk/dpll-tail.c
@@ -14,7 +14,7 @@ void uniphier_ld4_dpll_ssc_en(void)
 {
        u32 tmp;
 
-       tmp = readl(SC_DPLLCTRL);
+       tmp = readl(sc_base + SC_DPLLCTRL);
        tmp |= SC_DPLLCTRL_SSC_EN;
-       writel(tmp, SC_DPLLCTRL);
+       writel(tmp, sc_base + SC_DPLLCTRL);
 }

diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
index 67b8ee7..ea96d73 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
@@ -12,6 +12,7 @@
 #include <linux/io.h>
 #include <linux/sizes.h>
 
+#include "../sc64-regs.h"
 #include "pll.h"
 
 /* PLL type: SSC */
@@ -31,13 +32,9 @@
 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
                              unsigned int ssc_rate, unsigned int divn)
 {
-       void __iomem *base;
+       void __iomem *base = sc_base + reg_base;
        u32 tmp;
 
-       base = ioremap(reg_base, SZ_16);
-       if (!base)
-               return -ENOMEM;
-
        if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
                tmp = readl(base);      /* SSCPLLCTRL */
                tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
@@ -60,57 +57,39 @@ int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
        tmp |= SC_PLLCTRL2_NRSTDS;
        writel(tmp, base + 4);
 
-       iounmap(base);
-
        return 0;
 }
 
 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
 {
-       void __iomem *base;
+       void __iomem *base = sc_base + reg_base;
        u32 tmp;
 
-       base = ioremap(reg_base, SZ_16);
-       if (!base)
-               return -ENOMEM;
-
        tmp = readl(base);      /* SSCPLLCTRL */
        tmp |= SC_PLLCTRL_SSC_EN;
        writel(tmp, base);
 
-       iounmap(base);
-
        return 0;
 }
 
 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
 {
-       void __iomem *base;
+       void __iomem *base = sc_base + reg_base;
        u32 tmp;
 
-       base = ioremap(reg_base, SZ_16);
-       if (!base)
-               return -ENOMEM;
-
        tmp = readl(base + 8);  /* SSCPLLCTRL3 */
        tmp &= ~SC_PLLCTRL3_REGI_MASK;
        tmp |= FIELD_PREP(SC_PLLCTRL3_REGI_MASK, regi);
        writel(tmp, base + 8);
 
-       iounmap(base);
-
        return 0;
 }
 
 int uniphier_ld20_vpll27_init(unsigned long reg_base)
 {
-       void __iomem *base;
+       void __iomem *base = sc_base + reg_base;
        u32 tmp;
 
-       base = ioremap(reg_base, SZ_16);
-       if (!base)
-               return -ENOMEM;
-
        tmp = readl(base);              /* VPLL27CTRL */
        tmp |= SC_VPLL27CTRL_WP;        /* write protect off */
        writel(tmp, base);
@@ -123,25 +102,17 @@ int uniphier_ld20_vpll27_init(unsigned long reg_base)
        tmp &= ~SC_VPLL27CTRL_WP;       /* write protect on */
        writel(tmp, base);
 
-       iounmap(base);
-
        return 0;
 }
 
 int uniphier_ld20_dspll_init(unsigned long reg_base)
 {
-       void __iomem *base;
+       void __iomem *base = sc_base + reg_base;
        u32 tmp;
 
-       base = ioremap(reg_base, SZ_16);
-       if (!base)
-               return -ENOMEM;
-
        tmp = readl(base + 4);          /* DSPLLCTRL2 */
        tmp |= SC_DSPLLCTRL2_K_LD;
        writel(tmp, base + 4);
 
-       iounmap(base);
-
        return 0;
 }

diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c
index fd724f3..7f07e3e 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll-ld11.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld11.c
@@ -11,15 +11,15 @@
 #include "pll.h"
 
 /* PLL type: SSC */
-#define SC_CPLLCTRL    (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
-#define SC_SPLLCTRL    (SC_BASE_ADDR | 0x1410) /* misc */
-#define SC_MPLLCTRL    (SC_BASE_ADDR | 0x1430) /* DSP */
-#define SC_VSPLLCTRL   (SC_BASE_ADDR | 0x1440) /* Video codec, VPE etc. */
-#define SC_DPLLCTRL    (SC_BASE_ADDR | 0x1460) /* DDR memory */
+#define SC_CPLLCTRL    0x1400  /* CPU/ARM */
+#define SC_SPLLCTRL    0x1410  /* misc */
+#define SC_MPLLCTRL    0x1430  /* DSP */
+#define SC_VSPLLCTRL   0x1440  /* Video codec, VPE etc. */
+#define SC_DPLLCTRL    0x1460  /* DDR memory */
 
 /* PLL type: VPLL27 */
-#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+#define SC_VPLL27FCTRL 0x1500
+#define SC_VPLL27ACTRL 0x1520
 
 void uniphier_ld11_pll_init(void)
 {
@@ -40,6 +40,6 @@ void uniphier_ld11_pll_init(void)
        uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
        uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
 
-       writel(0, SC_CA53_GEARSET);     /* Gear0: CPLL/2 */
-       writel(SC_CA_GEARUPD, SC_CA53_GEARUPD);
+       writel(0, sc_base + SC_CA53_GEARSET);   /* Gear0: CPLL/2 */
+       writel(SC_CA_GEARUPD, sc_base + SC_CA53_GEARUPD);
 }

diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c
index 682bd1e..04b3312 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld20.c
@@ -11,23 +11,23 @@
 #include "pll.h"
 
 /* PLL type: SSC */
-#define SC_CPLLCTRL    (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
-#define SC_SPLLCTRL    (SC_BASE_ADDR | 0x1410) /* misc */
-#define SC_SPLL2CTRL   (SC_BASE_ADDR | 0x1420) /* DSP */
-#define SC_MPLLCTRL    (SC_BASE_ADDR | 0x1430) /* Video codec */
-#define SC_VPPLLCTRL   (SC_BASE_ADDR | 0x1440) /* VPE etc. */
-#define SC_GPPLLCTRL   (SC_BASE_ADDR | 0x1450) /* GPU/Mali */
-#define SC_DPLL0CTRL   (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */
-#define SC_DPLL1CTRL   (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */
-#define SC_DPLL2CTRL   (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */
+#define SC_CPLLCTRL    0x1400  /* CPU/ARM */
+#define SC_SPLLCTRL    0x1410  /* misc */
+#define SC_SPLL2CTRL   0x1420  /* DSP */
+#define SC_MPLLCTRL    0x1430  /* Video codec */
+#define SC_VPPLLCTRL   0x1440  /* VPE etc. */
+#define SC_GPPLLCTRL   0x1450  /* GPU/Mali */
+#define SC_DPLL0CTRL   0x1460  /* DDR memory 0 */
+#define SC_DPLL1CTRL   0x1470  /* DDR memory 1 */
+#define SC_DPLL2CTRL   0x1480  /* DDR memory 2 */
 
 /* PLL type: VPLL27 */
-#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+#define SC_VPLL27FCTRL 0x1500
+#define SC_VPLL27ACTRL 0x1520
 
 /* PLL type: DSPLL */
-#define SC_VPLL8KCTRL  (SC_BASE_ADDR | 0x1540)
-#define SC_A2PLLCTRL   (SC_BASE_ADDR | 0x15C0)
+#define SC_VPLL8KCTRL  0x1540
+#define SC_A2PLLCTRL   0x15C0
 
 void uniphier_ld20_pll_init(void)
 {

diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c
index 34f1c9c..c66031b 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll-ld4.c
+++ b/arch/arm/mach-uniphier/clk/pll-ld4.c
@@ -21,9 +21,9 @@ static void upll_init(void)
        clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
 
        /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
-       tmp = readl(SC_UPLLCTRL);
+       tmp = readl(sc_base + SC_UPLLCTRL);
        tmp &= ~0x18000000;
-       writel(tmp, SC_UPLLCTRL);
+       writel(tmp, sc_base + SC_UPLLCTRL);
 
        if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
                if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
@@ -38,18 +38,18 @@ static void upll_init(void)
                }
        }
 
-       writel(tmp, SC_UPLLCTRL);
+       writel(tmp, sc_base + SC_UPLLCTRL);
 
        /* set 1 to K_LD(UPLLCTRL.bit[27]) */
        tmp |= 0x08000000;
-       writel(tmp, SC_UPLLCTRL);
+       writel(tmp, sc_base + SC_UPLLCTRL);
 
        /* wait 10 usec */
        udelay(10);
 
        /* set 1 to SNRT(UPLLCTRL.bit[28]) */
        tmp |= 0x10000000;
-       writel(tmp, SC_UPLLCTRL);
+       writel(tmp, sc_base + SC_UPLLCTRL);
 }
 
 static void vpll_init(void)
@@ -60,88 +60,88 @@ static void vpll_init(void)
        clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
 
        /* set 1 to VPLA27WP and VPLA27WP */
-       tmp = readl(SC_VPLL27ACTRL);
+       tmp = readl(sc_base + SC_VPLL27ACTRL);
        tmp |= 0x00000001;
-       writel(tmp, SC_VPLL27ACTRL);
-       tmp = readl(SC_VPLL27BCTRL);
+       writel(tmp, sc_base + SC_VPLL27ACTRL);
+       tmp = readl(sc_base + SC_VPLL27BCTRL);
        tmp |= 0x00000001;
-       writel(tmp, SC_VPLL27BCTRL);
+       writel(tmp, sc_base + SC_VPLL27BCTRL);
 
        /* Set 0 to VPLA_K_LD and VPLB_K_LD */
-       tmp = readl(SC_VPLL27ACTRL3);
+       tmp = readl(sc_base + SC_VPLL27ACTRL3);
        tmp &= ~0x10000000;
-       writel(tmp, SC_VPLL27ACTRL3);
-       tmp = readl(SC_VPLL27BCTRL3);
+       writel(tmp, sc_base + SC_VPLL27ACTRL3);
+       tmp = readl(sc_base + SC_VPLL27BCTRL3);
        tmp &= ~0x10000000;
-       writel(tmp, SC_VPLL27BCTRL3);
+       writel(tmp, sc_base + SC_VPLL27BCTRL3);
 
        /* Set 0 to VPLA_SNRST and VPLB_SNRST */
-       tmp = readl(SC_VPLL27ACTRL2);
+       tmp = readl(sc_base + SC_VPLL27ACTRL2);
        tmp &= ~0x10000000;
-       writel(tmp, SC_VPLL27ACTRL2);
-       tmp = readl(SC_VPLL27BCTRL2);
+       writel(tmp, sc_base + SC_VPLL27ACTRL2);
+       tmp = readl(sc_base + SC_VPLL27BCTRL2);
        tmp &= ~0x10000000;
-       writel(tmp, SC_VPLL27BCTRL2);
+       writel(tmp, sc_base + SC_VPLL27BCTRL2);
 
        /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
-       tmp = readl(SC_VPLL27ACTRL2);
+       tmp = readl(sc_base + SC_VPLL27ACTRL2);
        tmp &= ~0x0000007f;
        tmp |= 0x00000020;
-       writel(tmp, SC_VPLL27ACTRL2);
-       tmp = readl(SC_VPLL27BCTRL2);
+       writel(tmp, sc_base + SC_VPLL27ACTRL2);
+       tmp = readl(sc_base + SC_VPLL27BCTRL2);
        tmp &= ~0x0000007f;
        tmp |= 0x00000020;
-       writel(tmp, SC_VPLL27BCTRL2);
+       writel(tmp, sc_base + SC_VPLL27BCTRL2);
 
        if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
            clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
                /* AXO: 25MHz */
-               tmp = readl(SC_VPLL27ACTRL3);
+               tmp = readl(sc_base + SC_VPLL27ACTRL3);
                tmp &= ~0x000fffff;
                tmp |= 0x00066664;
-               writel(tmp, SC_VPLL27ACTRL3);
-               tmp = readl(SC_VPLL27BCTRL3);
+               writel(tmp, sc_base + SC_VPLL27ACTRL3);
+               tmp = readl(sc_base + SC_VPLL27BCTRL3);
                tmp &= ~0x000fffff;
                tmp |= 0x00066664;
-               writel(tmp, SC_VPLL27BCTRL3);
+               writel(tmp, sc_base + SC_VPLL27BCTRL3);
        } else {
                /* AXO: default 24.576MHz */
-               tmp = readl(SC_VPLL27ACTRL3);
+               tmp = readl(sc_base + SC_VPLL27ACTRL3);
                tmp &= ~0x000fffff;
                tmp |= 0x000f5800;
-               writel(tmp, SC_VPLL27ACTRL3);
-               tmp = readl(SC_VPLL27BCTRL3);
+               writel(tmp, sc_base + SC_VPLL27ACTRL3);
+               tmp = readl(sc_base + SC_VPLL27BCTRL3);
                tmp &= ~0x000fffff;
                tmp |= 0x000f5800;
-               writel(tmp, SC_VPLL27BCTRL3);
+               writel(tmp, sc_base + SC_VPLL27BCTRL3);
        }
 
        /* Set 1 to VPLA_K_LD and VPLB_K_LD */
-       tmp = readl(SC_VPLL27ACTRL3);
+       tmp = readl(sc_base + SC_VPLL27ACTRL3);
        tmp |= 0x10000000;
-       writel(tmp, SC_VPLL27ACTRL3);
-       tmp = readl(SC_VPLL27BCTRL3);
+       writel(tmp, sc_base + SC_VPLL27ACTRL3);
+       tmp = readl(sc_base + SC_VPLL27BCTRL3);
        tmp |= 0x10000000;
-       writel(tmp, SC_VPLL27BCTRL3);
+       writel(tmp, sc_base + SC_VPLL27BCTRL3);
 
        /* wait 10 usec */
        udelay(10);
 
        /* Set 0 to VPLA_SNRST and VPLB_SNRST */
-       tmp = readl(SC_VPLL27ACTRL2);
+       tmp = readl(sc_base + SC_VPLL27ACTRL2);
        tmp |= 0x10000000;
-       writel(tmp, SC_VPLL27ACTRL2);
-       tmp = readl(SC_VPLL27BCTRL2);
+       writel(tmp, sc_base + SC_VPLL27ACTRL2);
+       tmp = readl(sc_base + SC_VPLL27BCTRL2);
        tmp |= 0x10000000;
-       writel(tmp, SC_VPLL27BCTRL2);
+       writel(tmp, sc_base + SC_VPLL27BCTRL2);
 
        /* set 0 to VPLA27WP and VPLA27WP */
-       tmp = readl(SC_VPLL27ACTRL);
+       tmp = readl(sc_base + SC_VPLL27ACTRL);
        tmp &= ~0x00000001;
-       writel(tmp, SC_VPLL27ACTRL);
-       tmp = readl(SC_VPLL27BCTRL);
+       writel(tmp, sc_base + SC_VPLL27ACTRL);
+       tmp = readl(sc_base + SC_VPLL27BCTRL);
        tmp |= ~0x00000001;
-       writel(tmp, SC_VPLL27BCTRL);
+       writel(tmp, sc_base + SC_VPLL27BCTRL);
 }
 
 void uniphier_ld4_pll_init(void)

diff --git a/arch/arm/mach-uniphier/clk/pll-pro4.c b/arch/arm/mach-uniphier/clk/pll-pro4.c
index 312a5fc..b7dc3e2 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll-pro4.c
+++ b/arch/arm/mach-uniphier/clk/pll-pro4.c
@@ -26,80 +26,80 @@ static void vpll_init(void)
                return;
 
        /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
-       tmp = readl(SC_VPLL27ACTRL);
+       tmp = readl(sc_base + SC_VPLL27ACTRL);
        tmp |= 0x00000001;
-       writel(tmp, SC_VPLL27ACTRL);
-       tmp = readl(SC_VPLL27BCTRL);
+       writel(tmp, sc_base + SC_VPLL27ACTRL);
+       tmp = readl(sc_base + SC_VPLL27BCTRL);
        tmp |= 0x00000001;
-       writel(tmp, SC_VPLL27BCTRL);
+       writel(tmp, sc_base + SC_VPLL27BCTRL);
 
        /* Unset VPLA_K_LD and VPLB_K_LD bit */
-       tmp = readl(SC_VPLL27ACTRL3);
+       tmp = readl(sc_base + SC_VPLL27ACTRL3);
        tmp &= ~0x10000000;
-       writel(tmp, SC_VPLL27ACTRL3);
-       tmp = readl(SC_VPLL27BCTRL3);
+       writel(tmp, sc_base + SC_VPLL27ACTRL3);
+       tmp = readl(sc_base + SC_VPLL27BCTRL3);
        tmp &= ~0x10000000;
-       writel(tmp, SC_VPLL27BCTRL3);
+       writel(tmp, sc_base + SC_VPLL27BCTRL3);
 
        /* Set VPLA_M and VPLB_M to 0x20 */
-       tmp = readl(SC_VPLL27ACTRL2);
+       tmp = readl(sc_base + SC_VPLL27ACTRL2);
        tmp &= ~0x0000007f;
        tmp |= 0x00000020;
-       writel(tmp, SC_VPLL27ACTRL2);
-       tmp = readl(SC_VPLL27BCTRL2);
+       writel(tmp, sc_base + SC_VPLL27ACTRL2);
+       tmp = readl(sc_base + SC_VPLL27BCTRL2);
        tmp &= ~0x0000007f;
        tmp |= 0x00000020;
-       writel(tmp, SC_VPLL27BCTRL2);
+       writel(tmp, sc_base + SC_VPLL27BCTRL2);
 
        if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
            clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
                /* Set VPLA_K and VPLB_K for AXO: 25MHz */
-               tmp = readl(SC_VPLL27ACTRL3);
+               tmp = readl(sc_base + SC_VPLL27ACTRL3);
                tmp &= ~0x000fffff;
                tmp |= 0x00066666;
-               writel(tmp, SC_VPLL27ACTRL3);
-               tmp = readl(SC_VPLL27BCTRL3);
+               writel(tmp, sc_base + SC_VPLL27ACTRL3);
+               tmp = readl(sc_base + SC_VPLL27BCTRL3);
                tmp &= ~0x000fffff;
                tmp |= 0x00066666;
-               writel(tmp, SC_VPLL27BCTRL3);
+               writel(tmp, sc_base + SC_VPLL27BCTRL3);
        } else {
                /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
-               tmp = readl(SC_VPLL27ACTRL3);
+               tmp = readl(sc_base + SC_VPLL27ACTRL3);
                tmp &= ~0x000fffff;
                tmp |= 0x000f5800;
-               writel(tmp, SC_VPLL27ACTRL3);
-               tmp = readl(SC_VPLL27BCTRL3);
+               writel(tmp, sc_base + SC_VPLL27ACTRL3);
+               tmp = readl(sc_base + SC_VPLL27BCTRL3);
                tmp &= ~0x000fffff;
                tmp |= 0x000f5800;
-               writel(tmp, SC_VPLL27BCTRL3);
+               writel(tmp, sc_base + SC_VPLL27BCTRL3);
        }
 
        /* wait 1 usec */
        udelay(1);
 
        /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
-       tmp = readl(SC_VPLL27ACTRL3);
+       tmp = readl(sc_base + SC_VPLL27ACTRL3);
        tmp |= 0x10000000;
-       writel(tmp, SC_VPLL27ACTRL3);
-       tmp = readl(SC_VPLL27BCTRL3);
+       writel(tmp, sc_base + SC_VPLL27ACTRL3);
+       tmp = readl(sc_base + SC_VPLL27BCTRL3);
        tmp |= 0x10000000;
-       writel(tmp, SC_VPLL27BCTRL3);
+       writel(tmp, sc_base + SC_VPLL27BCTRL3);
 
        /* Unset VPLA_SNRST and VPLB_SNRST bit */
-       tmp = readl(SC_VPLL27ACTRL2);
+       tmp = readl(sc_base + SC_VPLL27ACTRL2);
        tmp |= 0x10000000;
-       writel(tmp, SC_VPLL27ACTRL2);
-       tmp = readl(SC_VPLL27BCTRL2);
+       writel(tmp, sc_base + SC_VPLL27ACTRL2);
+       tmp = readl(sc_base + SC_VPLL27BCTRL2);
        tmp |= 0x10000000;
-       writel(tmp, SC_VPLL27BCTRL2);
+       writel(tmp, sc_base + SC_VPLL27BCTRL2);
 
        /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
-       tmp = readl(SC_VPLL27ACTRL);
+       tmp = readl(sc_base + SC_VPLL27ACTRL);
        tmp &= ~0x00000001;
-       writel(tmp, SC_VPLL27ACTRL);
-       tmp = readl(SC_VPLL27BCTRL);
+       writel(tmp, sc_base + SC_VPLL27ACTRL);
+       tmp = readl(sc_base + SC_VPLL27BCTRL);
        tmp &= ~0x00000001;
-       writel(tmp, SC_VPLL27BCTRL);
+       writel(tmp, sc_base + SC_VPLL27BCTRL);
 }
 
 void uniphier_pro4_pll_init(void)

diff --git a/arch/arm/mach-uniphier/clk/pll-pxs3.c b/arch/arm/mach-uniphier/clk/pll-pxs3.c
index 5a1b1d2..278f530 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll-pxs3.c
+++ b/arch/arm/mach-uniphier/clk/pll-pxs3.c
@@ -10,25 +10,25 @@
 #include "pll.h"
 
 /* PLL type: SSC */
-#define SC_CPLLCTRL    (SC_BASE_ADDR | 0x1400) /* CPU/ARM */
-#define SC_SPLLCTRL    (SC_BASE_ADDR | 0x1410) /* misc */
-#define SC_SPLL2CTRL   (SC_BASE_ADDR | 0x1420) /* DSP */
-#define SC_VPPLLCTRL   (SC_BASE_ADDR | 0x1430) /* VPE */
-#define SC_VGPLLCTRL   (SC_BASE_ADDR | 0x1440)
-#define SC_DECPLLCTRL  (SC_BASE_ADDR | 0x1450)
-#define SC_ENCPLLCTRL  (SC_BASE_ADDR | 0x1460)
-#define SC_PXFPLLCTRL  (SC_BASE_ADDR | 0x1470)
-#define SC_DPLL0CTRL   (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */
-#define SC_DPLL1CTRL   (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */
-#define SC_DPLL2CTRL   (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */
-#define SC_VSPLLCTRL   (SC_BASE_ADDR | 0x14c0)
+#define SC_CPLLCTRL    0x1400  /* CPU/ARM */
+#define SC_SPLLCTRL    0x1410  /* misc */
+#define SC_SPLL2CTRL   0x1420  /* DSP */
+#define SC_VPPLLCTRL   0x1430  /* VPE */
+#define SC_VGPLLCTRL   0x1440
+#define SC_DECPLLCTRL  0x1450
+#define SC_ENCPLLCTRL  0x1460
+#define SC_PXFPLLCTRL  0x1470
+#define SC_DPLL0CTRL   0x1480  /* DDR memory 0 */
+#define SC_DPLL1CTRL   0x1490  /* DDR memory 1 */
+#define SC_DPLL2CTRL   0x14a0  /* DDR memory 2 */
+#define SC_VSPLLCTRL   0x14c0
 
 /* PLL type: VPLL27 */
-#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500)
-#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520)
+#define SC_VPLL27FCTRL 0x1500
+#define SC_VPLL27ACTRL 0x1520
 
 /* PLL type: DSPLL */
-#define SC_VPLL8KCTRL  (SC_BASE_ADDR | 0x1540)
+#define SC_VPLL8KCTRL  0x1540
 
 void uniphier_pxs3_pll_init(void)
 {

diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c
index 22d2caa..f64ff39 100644 (file)
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-ld6b.c
@@ -22,9 +22,9 @@ unsigned int uniphier_ld6b_debug_uart_init(void)
        sg_set_pinsel(115, 0, 8, 4);    /* TXD1 -> TXD1 */
        sg_set_pinsel(113, 2, 8, 4);    /* SBO0 -> TXD2 */
 
-       tmp = readl(SC_CLKCTRL);
+       tmp = readl(sc_base + SC_CLKCTRL);
        tmp |= SC_CLKCTRL_CEN_PERI;
-       writel(tmp, SC_CLKCTRL);
+       writel(tmp, sc_base + SC_CLKCTRL);
 
        return DIV_ROUND_CLOSEST(UNIPHIER_LD6B_UART_CLK, 16 * CONFIG_BAUDRATE);
 }

diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c
index 9017a24..79c6c10 100644 (file)
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro4.c
@@ -22,9 +22,9 @@ unsigned int uniphier_pro4_debug_uart_init(void)
 
        writel(1, sg_base + SG_LOADPINCTRL);
 
-       tmp = readl(SC_CLKCTRL);
+       tmp = readl(sc_base + SC_CLKCTRL);
        tmp |= SC_CLKCTRL_CEN_PERI;
-       writel(tmp, SC_CLKCTRL);
+       writel(tmp, sc_base + SC_CLKCTRL);
 
        return DIV_ROUND_CLOSEST(UNIPHIER_PRO4_UART_CLK, 16 * CONFIG_BAUDRATE);
 }

diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c
index 8e4d15c..ef3b383 100644 (file)
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pro5.c
@@ -25,9 +25,9 @@ unsigned int uniphier_pro5_debug_uart_init(void)
 
        writel(1, sg_base + SG_LOADPINCTRL);
 
-       tmp = readl(SC_CLKCTRL);
+       tmp = readl(sc_base + SC_CLKCTRL);
        tmp |= SC_CLKCTRL_CEN_PERI;
-       writel(tmp, SC_CLKCTRL);
+       writel(tmp, sc_base + SC_CLKCTRL);
 
        return DIV_ROUND_CLOSEST(UNIPHIER_PRO5_UART_CLK, 16 * CONFIG_BAUDRATE);
 }

diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c
index 5d50c4f..ee8caad 100644 (file)
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart-pxs2.c
@@ -23,9 +23,9 @@ unsigned int uniphier_pxs2_debug_uart_init(void)
        sg_set_pinsel(113, 8, 8, 4);    /* TXD2 -> TXD2 */
        sg_set_pinsel(219, 8, 8, 4);    /* TXD3 -> TXD3 */
 
-       tmp = readl(SC_CLKCTRL);
+       tmp = readl(sc_base + SC_CLKCTRL);
        tmp |= SC_CLKCTRL_CEN_PERI;
-       writel(tmp, SC_CLKCTRL);
+       writel(tmp, sc_base + SC_CLKCTRL);
 
        return DIV_ROUND_CLOSEST(UNIPHIER_PXS2_UART_CLK, 16 * CONFIG_BAUDRATE);
 }

diff --git a/arch/arm/mach-uniphier/reset.c b/arch/arm/mach-uniphier/reset.c
index 28c95e2..31685d0 100644 (file)
--- a/arch/arm/mach-uniphier/reset.c
+++ b/arch/arm/mach-uniphier/reset.c
@@ -22,14 +22,14 @@ void __SECURE reset_cpu(unsigned long ignored)
 {
        u32 tmp;
 
-       writel(5, SC_IRQTIMSET); /* default value */
+       writel(5, sc_base + SC_IRQTIMSET); /* default value */
 
-       tmp  = readl(SC_SLFRSTSEL);
+       tmp  = readl(sc_base + SC_SLFRSTSEL);
        tmp &= ~0x3; /* mask [1:0] */
        tmp |= 0x0;  /* XRST reboot */
-       writel(tmp, SC_SLFRSTSEL);
+       writel(tmp, sc_base + SC_SLFRSTSEL);
 
-       tmp = readl(SC_SLFRSTCTL);
+       tmp = readl(sc_base + SC_SLFRSTCTL);
        tmp |= 0x1;
-       writel(tmp, SC_SLFRSTCTL);
+       writel(tmp, sc_base + SC_SLFRSTCTL);
 }

diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h
index 28de19c..e43116e 100644 (file)
--- a/arch/arm/mach-uniphier/sc-regs.h
+++ b/arch/arm/mach-uniphier/sc-regs.h
@@ -10,31 +10,36 @@
 #ifndef ARCH_SC_REGS_H
 #define ARCH_SC_REGS_H
 
-#define SC_BASE_ADDR                   0x61840000
+#ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+#define sc_base                        ((void __iomem *)SC_BASE)
+#endif
 
-#define SC_DPLLCTRL                    (SC_BASE_ADDR | 0x1200)
+#define SC_BASE                        0x61840000
+
+#define SC_DPLLCTRL            0x1200
 #define SC_DPLLCTRL_SSC_EN             (0x1 << 31)
 #define SC_DPLLCTRL_FOUTMODE_MASK        (0xf << 16)
 #define SC_DPLLCTRL_SSC_RATE           (0x1 << 15)
 
-#define SC_DPLLCTRL2                   (SC_BASE_ADDR | 0x1204)
+#define SC_DPLLCTRL2           0x1204
 #define SC_DPLLCTRL2_NRSTDS            (0x1 << 28)
 
-#define SC_DPLLCTRL3                   (SC_BASE_ADDR | 0x1208)
+#define SC_DPLLCTRL3           0x1208
 #define SC_DPLLCTRL3_LPFSEL_COEF2      (0x0 << 31)
 #define SC_DPLLCTRL3_LPFSEL_COEF3      (0x1 << 31)
 
-#define SC_UPLLCTRL                    (SC_BASE_ADDR | 0x1210)
+#define SC_UPLLCTRL            0x1210
 
-#define SC_VPLL27ACTRL                 (SC_BASE_ADDR | 0x1270)
-#define SC_VPLL27ACTRL2                        (SC_BASE_ADDR | 0x1274)
-#define SC_VPLL27ACTRL3                        (SC_BASE_ADDR | 0x1278)
+#define SC_VPLL27ACTRL         0x1270
+#define SC_VPLL27ACTRL2                0x1274
+#define SC_VPLL27ACTRL3                0x1278
 
-#define SC_VPLL27BCTRL                 (SC_BASE_ADDR | 0x1290)
-#define SC_VPLL27BCTRL2                        (SC_BASE_ADDR | 0x1294)
-#define SC_VPLL27BCTRL3                        (SC_BASE_ADDR | 0x1298)
+#define SC_VPLL27BCTRL         0x1290
+#define SC_VPLL27BCTRL2                0x1294
+#define SC_VPLL27BCTRL3                0x1298
 
-#define SC_RSTCTRL                     (SC_BASE_ADDR | 0x2000)
+#define SC_RSTCTRL             0x2000
 #define SC_RSTCTRL_NRST_USB3B0         (0x1 << 17)     /* USB3 #0 bus */
 #define SC_RSTCTRL_NRST_USB3C0         (0x1 << 16)     /* USB3 #0 core */
 #define SC_RSTCTRL_NRST_ETHER          (0x1 << 12)
@@ -44,14 +49,14 @@
 #define SC_RSTCTRL_NRST_UMC0           (0x1 <<  4)
 #define SC_RSTCTRL_NRST_NAND           (0x1 <<  2)
 
-#define SC_RSTCTRL2                    (SC_BASE_ADDR | 0x2004)
+#define SC_RSTCTRL2            0x2004
 #define SC_RSTCTRL2_NRST_USB3B1                (0x1 << 17)     /* USB3 #1 bus */
 #define SC_RSTCTRL2_NRST_USB3C1                (0x1 << 16)     /* USB3 #1 core */
 
-#define SC_RSTCTRL3                    (SC_BASE_ADDR | 0x2008)
+#define SC_RSTCTRL3            0x2008
 
 /* Pro5 or newer */
-#define SC_RSTCTRL4                    (SC_BASE_ADDR | 0x200c)
+#define SC_RSTCTRL4            0x200c
 #define SC_RSTCTRL4_NRST_UMCSB         (0x1 << 12)     /* UMC system bus */
 #define SC_RSTCTRL4_NRST_UMCA2         (0x1 << 10)     /* UMC ch2 standby */
 #define SC_RSTCTRL4_NRST_UMCA1         (0x1 <<  9)     /* UMC ch1 standby */
@@ -60,11 +65,11 @@
 #define SC_RSTCTRL4_NRST_UMC31         (0x1 <<  5)     /* UMC ch1 */
 #define SC_RSTCTRL4_NRST_UMC30         (0x1 <<  4)     /* UMC ch0 */
 
-#define SC_RSTCTRL5                    (SC_BASE_ADDR | 0x2010)
+#define SC_RSTCTRL5            0x2010
 
-#define SC_RSTCTRL6                    (SC_BASE_ADDR | 0x2014)
+#define SC_RSTCTRL6            0x2014
 
-#define SC_CLKCTRL                     (SC_BASE_ADDR | 0x2104)
+#define SC_CLKCTRL             0x2104
 #define SC_CLKCTRL_CEN_USB31           (0x1 << 17)     /* USB3 #1 */
 #define SC_CLKCTRL_CEN_USB30           (0x1 << 16)     /* USB3 #0 */
 #define SC_CLKCTRL_CEN_ETHER           (0x1 << 12)
@@ -76,15 +81,15 @@
 #define SC_CLKCTRL_CEN_PERI            (0x1 <<  0)
 
 /* Pro5 or newer */
-#define SC_CLKCTRL4                    (SC_BASE_ADDR | 0x210c)
+#define SC_CLKCTRL4            0x210c
 #define SC_CLKCTRL4_CEN_UMCSB          (0x1 << 12)     /* UMC system bus */
 #define SC_CLKCTRL4_CEN_UMC2           (0x1 <<  2)     /* UMC ch2 */
 #define SC_CLKCTRL4_CEN_UMC1           (0x1 <<  1)     /* UMC ch1 */
 #define SC_CLKCTRL4_CEN_UMC0           (0x1 <<  0)     /* UMC ch0 */
 
 /* System reset control register */
-#define SC_IRQTIMSET                   (SC_BASE_ADDR | 0x3000)
-#define SC_SLFRSTSEL                   (SC_BASE_ADDR | 0x3010)
-#define SC_SLFRSTCTL                   (SC_BASE_ADDR | 0x3014)
+#define SC_IRQTIMSET           0x3000
+#define SC_SLFRSTSEL           0x3010
+#define SC_SLFRSTCTL           0x3014
 
 #endif /* ARCH_SC_REGS_H */

diff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h
index 83f34e3..1f3b41a 100644 (file)
--- a/arch/arm/mach-uniphier/sc64-regs.h
+++ b/arch/arm/mach-uniphier/sc64-regs.h
@@ -9,28 +9,33 @@
 #ifndef SC64_REGS_H
 #define SC64_REGS_H
 
-#define SC_BASE_ADDR           0x61840000
+#ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+#define sc_base                        ((void __iomem *)SC_BASE)
+#endif
 
-#define SC_RSTCTRL             (SC_BASE_ADDR | 0x2000)
-#define SC_RSTCTRL3            (SC_BASE_ADDR | 0x2008)
-#define SC_RSTCTRL4            (SC_BASE_ADDR | 0x200c)
-#define SC_RSTCTRL5            (SC_BASE_ADDR | 0x2010)
-#define SC_RSTCTRL6            (SC_BASE_ADDR | 0x2014)
-#define SC_RSTCTRL7            (SC_BASE_ADDR | 0x2018)
+#define SC_BASE                        0x61840000
 
-#define SC_CLKCTRL             (SC_BASE_ADDR | 0x2100)
-#define SC_CLKCTRL3            (SC_BASE_ADDR | 0x2108)
-#define SC_CLKCTRL4            (SC_BASE_ADDR | 0x210c)
-#define SC_CLKCTRL5            (SC_BASE_ADDR | 0x2110)
-#define SC_CLKCTRL6            (SC_BASE_ADDR | 0x2114)
-#define SC_CLKCTRL7            (SC_BASE_ADDR | 0x2118)
+#define SC_RSTCTRL             0x2000
+#define SC_RSTCTRL3            0x2008
+#define SC_RSTCTRL4            0x200c
+#define SC_RSTCTRL5            0x2010
+#define SC_RSTCTRL6            0x2014
+#define SC_RSTCTRL7            0x2018
 
-#define SC_CA72_GEARST         (SC_BASE_ADDR | 0x8000)
-#define SC_CA72_GEARSET                (SC_BASE_ADDR | 0x8004)
-#define SC_CA72_GEARUPD                (SC_BASE_ADDR | 0x8008)
-#define SC_CA53_GEARST         (SC_BASE_ADDR | 0x8080)
-#define SC_CA53_GEARSET                (SC_BASE_ADDR | 0x8084)
-#define SC_CA53_GEARUPD                (SC_BASE_ADDR | 0x8088)
+#define SC_CLKCTRL             0x2100
+#define SC_CLKCTRL3            0x2108
+#define SC_CLKCTRL4            0x210c
+#define SC_CLKCTRL5            0x2110
+#define SC_CLKCTRL6            0x2114
+#define SC_CLKCTRL7            0x2118
+
+#define SC_CA72_GEARST         0x8000
+#define SC_CA72_GEARSET                0x8004
+#define SC_CA72_GEARUPD                0x8008
+#define SC_CA53_GEARST         0x8080
+#define SC_CA53_GEARSET                0x8084
+#define SC_CA53_GEARUPD                0x8088
 #define   SC_CA_GEARUPD                        (1 << 0)
 
 #endif /* SC64_REGS_H */