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soc/tegra: fuse: Add RAM code reader helper
authorMikko Perttunen <mperttunen@nvidia.com>
Thu, 12 Mar 2015 14:47:55 +0000 (15:47 +0100)
committerThierry Reding <treding@nvidia.com>
Mon, 4 May 2015 12:21:21 +0000 (14:21 +0200)
Needed for the EMC and MC drivers to know what timings from the DT to
use.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

No differences found
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